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Add bd82x6x PCH functions to SMM 

Add the PCH function to SMM for follow-on SMM patches that
require these functions.

Change-Id: I7f3a512c5e98446e835b59934d63a99e8af15280
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/2758
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit is contained in:
Marc Jones 2013-02-11 14:36:35 -07:00 committed by Ronald G. Minnich
parent e6c3b1d30d
commit 783f226208
3 changed files with 91 additions and 69 deletions
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2
src/southbridge/intel/bd82x6x/Makefile.inc
View File

@ -42,7 +42,7 @@ ramstage-y += spi.c
smm-$(CONFIG_SPI_FLASH_SMM) += spi.c
ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me.c me_8.x.c finalize.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me.c me_8.x.c finalize.c pch.c
romstage-y += early_usb.c early_smbus.c early_me.c me_status.c gpio.c
romstage-$(CONFIG_USBDEBUG) += usb_debug.c

150
src/southbridge/intel/bd82x6x/pch.c
View File

@ -21,8 +21,14 @@
#include <console/console.h>
#include <delay.h>
#ifdef __SMM__
#include <arch/io.h>
#include <arch/romcc_io.h>
#include <device/pci_def.h>
#else /* !__SMM__ */
#include <device/device.h>
#include <device/pci.h>
#endif
#include "pch.h"
static int pch_revision_id = -1;
@ -30,19 +36,31 @@ static int pch_type = -1;
int pch_silicon_revision(void)
{
device_t dev;
#ifdef __SMM__
dev = PCI_DEV(0, 0x1f, 0);
#else
dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
#endif
if (pch_revision_id < 0)
pch_revision_id = pci_read_config8(
dev_find_slot(0, PCI_DEVFN(0x1f, 0)),
PCI_REVISION_ID);
pch_revision_id = pci_read_config8(dev, PCI_REVISION_ID);
return pch_revision_id;
}
int pch_silicon_type(void)
{
device_t dev;
#ifdef __SMM__
dev = PCI_DEV(0, 0x1f, 0);
#else
dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
#endif
if (pch_type < 0)
pch_type = pci_read_config8(
dev_find_slot(0, PCI_DEVFN(0x1f, 0)),
PCI_DEVICE_ID + 1);
pch_type = pci_read_config8(dev, PCI_DEVICE_ID + 1);
return pch_type;
}
@ -71,65 +89,6 @@ int pch_silicon_supported(int type, int rev)
return 0;
}
/* Set bit in Function Disble register to hide this device */
static void pch_hide_devfn(unsigned devfn)
{
switch (devfn) {
case PCI_DEVFN(22, 0): /* MEI #1 */
RCBA32_OR(FD2, PCH_DISABLE_MEI1);
break;
case PCI_DEVFN(22, 1): /* MEI #2 */
RCBA32_OR(FD2, PCH_DISABLE_MEI2);
break;
case PCI_DEVFN(22, 2): /* IDE-R */
RCBA32_OR(FD2, PCH_DISABLE_IDER);
break;
case PCI_DEVFN(22, 3): /* KT */
RCBA32_OR(FD2, PCH_DISABLE_KT);
break;
case PCI_DEVFN(25, 0): /* Gigabit Ethernet */
RCBA32_OR(BUC, PCH_DISABLE_GBE);
break;
case PCI_DEVFN(26, 0): /* EHCI #2 */
RCBA32_OR(FD, PCH_DISABLE_EHCI2);
break;
case PCI_DEVFN(27, 0): /* HD Audio Controller */
RCBA32_OR(FD, PCH_DISABLE_HD_AUDIO);
break;
case PCI_DEVFN(28, 0): /* PCI Express Root Port 1 */
case PCI_DEVFN(28, 1): /* PCI Express Root Port 2 */
case PCI_DEVFN(28, 2): /* PCI Express Root Port 3 */
case PCI_DEVFN(28, 3): /* PCI Express Root Port 4 */
case PCI_DEVFN(28, 4): /* PCI Express Root Port 5 */
case PCI_DEVFN(28, 5): /* PCI Express Root Port 6 */
case PCI_DEVFN(28, 6): /* PCI Express Root Port 7 */
case PCI_DEVFN(28, 7): /* PCI Express Root Port 8 */
RCBA32_OR(FD, PCH_DISABLE_PCIE(PCI_FUNC(devfn)));
break;
case PCI_DEVFN(29, 0): /* EHCI #1 */
RCBA32_OR(FD, PCH_DISABLE_EHCI1);
break;
case PCI_DEVFN(30, 0): /* PCI-to-PCI Bridge */
RCBA32_OR(FD, PCH_DISABLE_P2P);
break;
case PCI_DEVFN(31, 0): /* LPC */
RCBA32_OR(FD, PCH_DISABLE_LPC);
break;
case PCI_DEVFN(31, 2): /* SATA #1 */
RCBA32_OR(FD, PCH_DISABLE_SATA1);
break;
case PCI_DEVFN(31, 3): /* SMBUS */
RCBA32_OR(FD, PCH_DISABLE_SMBUS);
break;
case PCI_DEVFN(31, 5): /* SATA #22 */
RCBA32_OR(FD, PCH_DISABLE_SATA2);
break;
case PCI_DEVFN(31, 6): /* Thermal Subsystem */
RCBA32_OR(FD, PCH_DISABLE_THERMAL);
break;
}
}
#define IOBP_RETRY 1000
static inline int iobp_poll(void)
{
@ -191,6 +150,66 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue)
return;
}
#ifndef __SMM__
/* Set bit in Function Disble register to hide this device */
static void pch_hide_devfn(unsigned devfn)
{
switch (devfn) {
case PCI_DEVFN(22, 0): /* MEI #1 */
RCBA32_OR(FD2, PCH_DISABLE_MEI1);
break;
case PCI_DEVFN(22, 1): /* MEI #2 */
RCBA32_OR(FD2, PCH_DISABLE_MEI2);
break;
case PCI_DEVFN(22, 2): /* IDE-R */
RCBA32_OR(FD2, PCH_DISABLE_IDER);
break;
case PCI_DEVFN(22, 3): /* KT */
RCBA32_OR(FD2, PCH_DISABLE_KT);
break;
case PCI_DEVFN(25, 0): /* Gigabit Ethernet */
RCBA32_OR(BUC, PCH_DISABLE_GBE);
break;
case PCI_DEVFN(26, 0): /* EHCI #2 */
RCBA32_OR(FD, PCH_DISABLE_EHCI2);
break;
case PCI_DEVFN(27, 0): /* HD Audio Controller */
RCBA32_OR(FD, PCH_DISABLE_HD_AUDIO);
break;
case PCI_DEVFN(28, 0): /* PCI Express Root Port 1 */
case PCI_DEVFN(28, 1): /* PCI Express Root Port 2 */
case PCI_DEVFN(28, 2): /* PCI Express Root Port 3 */
case PCI_DEVFN(28, 3): /* PCI Express Root Port 4 */
case PCI_DEVFN(28, 4): /* PCI Express Root Port 5 */
case PCI_DEVFN(28, 5): /* PCI Express Root Port 6 */
case PCI_DEVFN(28, 6): /* PCI Express Root Port 7 */
case PCI_DEVFN(28, 7): /* PCI Express Root Port 8 */
RCBA32_OR(FD, PCH_DISABLE_PCIE(PCI_FUNC(devfn)));
break;
case PCI_DEVFN(29, 0): /* EHCI #1 */
RCBA32_OR(FD, PCH_DISABLE_EHCI1);
break;
case PCI_DEVFN(30, 0): /* PCI-to-PCI Bridge */
RCBA32_OR(FD, PCH_DISABLE_P2P);
break;
case PCI_DEVFN(31, 0): /* LPC */
RCBA32_OR(FD, PCH_DISABLE_LPC);
break;
case PCI_DEVFN(31, 2): /* SATA #1 */
RCBA32_OR(FD, PCH_DISABLE_SATA1);
break;
case PCI_DEVFN(31, 3): /* SMBUS */
RCBA32_OR(FD, PCH_DISABLE_SMBUS);
break;
case PCI_DEVFN(31, 5): /* SATA #22 */
RCBA32_OR(FD, PCH_DISABLE_SATA2);
break;
case PCI_DEVFN(31, 6): /* Thermal Subsystem */
RCBA32_OR(FD, PCH_DISABLE_THERMAL);
break;
}
}
/* Check if any port in set X to X+3 is enabled */
static int pch_pcie_check_set_enabled(device_t dev)
{
@ -408,3 +427,4 @@ struct chip_operations southbridge_intel_bd82x6x_ops = {
CHIP_NAME("Intel Series 6/7 (Cougar Point/Panther Point) Southbridge")
.enable_dev = pch_enable,
};
#endif

8
src/southbridge/intel/bd82x6x/pch.h
View File

@ -57,17 +57,19 @@ void intel_pch_finalize_smm(void);
#endif
#if !defined(__ASSEMBLER__) && !defined(__ROMCC__)
#if !defined(__PRE_RAM__) && !defined(__SMM__)
#if !defined(__PRE_RAM__)
#if !defined(__SMM__)
#include "chip.h"
void pch_enable(device_t dev);
#endif
int pch_silicon_revision(void);
int pch_silicon_type(void);
int pch_silicon_supported(int type, int rev);
void pch_enable(device_t dev);
void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue);
#if CONFIG_ELOG
void pch_log_state(void);
#endif
#else
#else /* __PRE_RAM__ */
void enable_smbus(void);
void enable_usb_bar(void);
int smbus_read_byte(unsigned device, unsigned address);