cpu/intel/common: Add CPU_INTEL_COMMON_TIMEBASE
To add a common tsc_freq_mhz() implementation, we need to guard againts soc-specific duplicate definitions. Change-Id: I37a34651d9e7d823ad5689d30739294358a97e31 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31341 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: David Guckian Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -19,4 +19,7 @@ config SET_IA32_FC_LOCK_BIT
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However, leaving the lock bit unset will break Windows' detection of
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VMX support and built-in virtualization features like Hyper-V.
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config CPU_INTEL_COMMON_TIMEBASE
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bool
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endif
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@ -1,5 +1,10 @@
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ramstage-y += common_init.c
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romstage-$(CONFIG_UDELAY_LAPIC) += fsb.c
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ramstage-$(CONFIG_UDELAY_LAPIC) += fsb.c
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postcar-$(CONFIG_UDELAY_LAPIC) += fsb.c
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ifeq ($(CONFIG_CPU_INTEL_COMMON_TIMEBASE),y)
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bootblock-y += fsb.c
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verstage-y += fsb.c
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romstage-y += fsb.c
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postcar-y += fsb.c
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ramstage-y += fsb.c
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smm-y += fsb.c
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endif
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@ -33,6 +33,7 @@ config CPU_SPECIFIC_OPTIONS
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select TSC_SYNC_MFENCE
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select LAPIC_MONOTONIC_TIMER
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select CPU_INTEL_COMMON
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select CPU_INTEL_COMMON_TIMEBASE
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select NO_SMM
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# Microcode header files are delivered in FSP package
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@ -10,3 +10,4 @@ config CPU_INTEL_MODEL_1067X
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select TSC_SYNC_MFENCE
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select SUPPORT_CPU_UCODE_IN_CBFS
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select CPU_INTEL_COMMON
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select CPU_INTEL_COMMON_TIMEBASE
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@ -13,6 +13,7 @@ config CPU_INTEL_MODEL_106CX
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select SUPPORT_CPU_UCODE_IN_CBFS
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select SERIALIZED_SMM_INITIALIZATION
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select CPU_INTEL_COMMON
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select CPU_INTEL_COMMON_TIMEBASE
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if CPU_INTEL_MODEL_106CX
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@ -11,3 +11,4 @@ config CPU_INTEL_MODEL_6EX
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select TSC_SYNC_MFENCE
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select SUPPORT_CPU_UCODE_IN_CBFS
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select CPU_INTEL_COMMON
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select CPU_INTEL_COMMON_TIMEBASE
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@ -11,3 +11,4 @@ config CPU_INTEL_MODEL_6FX
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select TSC_SYNC_MFENCE
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select SUPPORT_CPU_UCODE_IN_CBFS
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select CPU_INTEL_COMMON
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select CPU_INTEL_COMMON_TIMEBASE
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