cpu/intel/common: Add CPU_INTEL_COMMON_TIMEBASE

To add a common tsc_freq_mhz() implementation, we need
to guard againts soc-specific duplicate definitions.

Change-Id: I37a34651d9e7d823ad5689d30739294358a97e31
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31341
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: David Guckian
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kyösti Mälkki 2019-02-11 11:33:36 +02:00 committed by Patrick Georgi
parent 783982751d
commit 7841a7f824
7 changed files with 16 additions and 3 deletions

View File

@ -19,4 +19,7 @@ config SET_IA32_FC_LOCK_BIT
However, leaving the lock bit unset will break Windows' detection of However, leaving the lock bit unset will break Windows' detection of
VMX support and built-in virtualization features like Hyper-V. VMX support and built-in virtualization features like Hyper-V.
config CPU_INTEL_COMMON_TIMEBASE
bool
endif endif

View File

@ -1,5 +1,10 @@
ramstage-y += common_init.c ramstage-y += common_init.c
romstage-$(CONFIG_UDELAY_LAPIC) += fsb.c
ramstage-$(CONFIG_UDELAY_LAPIC) += fsb.c ifeq ($(CONFIG_CPU_INTEL_COMMON_TIMEBASE),y)
postcar-$(CONFIG_UDELAY_LAPIC) += fsb.c bootblock-y += fsb.c
verstage-y += fsb.c
romstage-y += fsb.c
postcar-y += fsb.c
ramstage-y += fsb.c
smm-y += fsb.c smm-y += fsb.c
endif

View File

@ -33,6 +33,7 @@ config CPU_SPECIFIC_OPTIONS
select TSC_SYNC_MFENCE select TSC_SYNC_MFENCE
select LAPIC_MONOTONIC_TIMER select LAPIC_MONOTONIC_TIMER
select CPU_INTEL_COMMON select CPU_INTEL_COMMON
select CPU_INTEL_COMMON_TIMEBASE
select NO_SMM select NO_SMM
# Microcode header files are delivered in FSP package # Microcode header files are delivered in FSP package

View File

@ -10,3 +10,4 @@ config CPU_INTEL_MODEL_1067X
select TSC_SYNC_MFENCE select TSC_SYNC_MFENCE
select SUPPORT_CPU_UCODE_IN_CBFS select SUPPORT_CPU_UCODE_IN_CBFS
select CPU_INTEL_COMMON select CPU_INTEL_COMMON
select CPU_INTEL_COMMON_TIMEBASE

View File

@ -13,6 +13,7 @@ config CPU_INTEL_MODEL_106CX
select SUPPORT_CPU_UCODE_IN_CBFS select SUPPORT_CPU_UCODE_IN_CBFS
select SERIALIZED_SMM_INITIALIZATION select SERIALIZED_SMM_INITIALIZATION
select CPU_INTEL_COMMON select CPU_INTEL_COMMON
select CPU_INTEL_COMMON_TIMEBASE
if CPU_INTEL_MODEL_106CX if CPU_INTEL_MODEL_106CX

View File

@ -11,3 +11,4 @@ config CPU_INTEL_MODEL_6EX
select TSC_SYNC_MFENCE select TSC_SYNC_MFENCE
select SUPPORT_CPU_UCODE_IN_CBFS select SUPPORT_CPU_UCODE_IN_CBFS
select CPU_INTEL_COMMON select CPU_INTEL_COMMON
select CPU_INTEL_COMMON_TIMEBASE

View File

@ -11,3 +11,4 @@ config CPU_INTEL_MODEL_6FX
select TSC_SYNC_MFENCE select TSC_SYNC_MFENCE
select SUPPORT_CPU_UCODE_IN_CBFS select SUPPORT_CPU_UCODE_IN_CBFS
select CPU_INTEL_COMMON select CPU_INTEL_COMMON
select CPU_INTEL_COMMON_TIMEBASE