sb/intel/bd82x6x/acpi: Convert to ASL 2.0
Change-Id: Ib587d7a982852e7123e43337407ef20d96811719 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50327 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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@ -111,53 +111,53 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
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/* Set flag to enable USB charging in S3 */
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Method (S3UE)
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{
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Store (One, \S3U0)
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Store (One, \S3U1)
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\S3U0 = 1
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\S3U1 = 1
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}
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/* Set flag to disable USB charging in S3 */
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Method (S3UD)
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{
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Store (Zero, \S3U0)
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Store (Zero, \S3U1)
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\S3U0 = 0
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\S3U1 = 0
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}
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/* Set flag to enable USB charging in S5 */
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Method (S5UE)
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{
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Store (One, \S5U0)
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Store (One, \S5U1)
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\S5U0 = 1
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\S5U1 = 1
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}
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/* Set flag to disable USB charging in S5 */
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Method (S5UD)
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{
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Store (Zero, \S5U0)
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Store (Zero, \S5U1)
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\S5U0 = 0
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\S5U1 = 0
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}
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/* Set flag to enable 3G module in S3 */
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Method (S3GE)
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{
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Store (One, \S33G)
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\S33G = 1
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}
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/* Set flag to disable 3G module in S3 */
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Method (S3GD)
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{
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Store (Zero, \S33G)
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\S33G = 0
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}
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/* Set XHCI Mode enable */
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Method (XHCE)
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{
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Store (One, \XHCI)
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\XHCI = 1
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}
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/* Set XHCI Mode disable */
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Method (XHCD)
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{
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Store (Zero, \XHCI)
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\XHCI = 0
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}
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External (\_TZ.SKIN)
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@ -179,46 +179,46 @@ Method (TZUP)
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/* Update Fan 0 thresholds */
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Method (F0UT, 2)
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{
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Store (Arg0, \F0OF)
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Store (Arg1, \F0ON)
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\F0OF = Arg0
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\F0ON = Arg1
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TZUP ()
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}
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/* Update Fan 1 thresholds */
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Method (F1UT, 2)
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{
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Store (Arg0, \F1OF)
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Store (Arg1, \F1ON)
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\F1OF = Arg0
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\F1ON = Arg1
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TZUP ()
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}
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/* Update Fan 2 thresholds */
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Method (F2UT, 2)
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{
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Store (Arg0, \F2OF)
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Store (Arg1, \F2ON)
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\F2OF = Arg0
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\F2ON = Arg1
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TZUP ()
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}
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/* Update Fan 3 thresholds */
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Method (F3UT, 2)
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{
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Store (Arg0, \F3OF)
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Store (Arg1, \F3ON)
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\F3OF = Arg0
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\F3ON = Arg1
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TZUP ()
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}
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/* Update Fan 4 thresholds */
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Method (F4UT, 2)
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{
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Store (Arg0, \F4OF)
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Store (Arg1, \F4ON)
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\F4OF = Arg0
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\F4ON = Arg1
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TZUP ()
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}
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/* Update Temperature Sensor ID */
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Method (TMPU, 1)
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{
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Store (Arg0, \TMPS)
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\TMPS = Arg0
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TZUP ()
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}
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@ -37,12 +37,12 @@ Device (EHC1)
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})
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// REV: Revision 0x02 for ACPI 5.0
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CreateField (DerefOf (Index (PCKG, Zero)), Zero, 0x07, REV)
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Store (0x02, REV)
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CreateField (DerefOf (PCKG [0]), 0, 0x07, REV)
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REV = 0x02
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// VISI: Port visibility to user per port
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CreateField (DerefOf (Index (PCKG, Zero)), 0x40, One, VISI)
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Store (Arg0, VISI)
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CreateField (DerefOf (PCKG [0]), 0x40, 1, VISI)
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VISI = Arg0
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Return (PCKG)
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}
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@ -90,12 +90,12 @@ Device (EHC2)
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})
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// REV: Revision 0x02 for ACPI 5.0
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CreateField (DerefOf (Index (PCKG, Zero)), Zero, 0x07, REV)
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Store (0x02, REV)
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CreateField (DerefOf (PCKG [0]), 0, 0x07, REV)
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REV = 0x02
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// VISI: Port visibility to user per port
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CreateField (DerefOf (Index (PCKG, Zero)), 0x40, One, VISI)
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Store (Arg0, VISI)
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CreateField (DerefOf (PCKG [0]), 0x40, 1, VISI)
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VISI = Arg0
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Return (PCKG)
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}
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@ -137,38 +137,38 @@ Device (XHC)
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CreateDWordField(Arg1,0,CDW1)
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// Check revision
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If(LNotEqual(Arg0,One)) {
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If(Arg0 != 1) {
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// Set unknown revision bit
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Or(CDW1,0x8,CDW1)
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CDW1 |= 8
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}
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// Set failure if xHCI is disabled by coreboot
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If(LEqual(XHCI, 0)) {
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Or(CDW1,0x2,CDW1)
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If(XHCI == 0) {
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CDW1 |= 2
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}
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// Query flag clear and xHCI in auto mode
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If(LAnd(LNot(And(CDW1,0x1)),LOr(LEqual(XHCI ,2), LEqual(XHCI ,3)))) {
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Store ("XHCI Switch", Debug)
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Store(Zero, Local0)
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And(XPRT, 0x3, Local0)
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If(LOr(LEqual(Local0, 0), LEqual(Local0, 1))) {
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Store(0xF, Local1)
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If(!(CDW1 & 0x1) && (XHCI == 2 || XHCI == 3)) {
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Debug = "XHCI Switch"
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Local0 = 0
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Local0 = XPRT & 0x03
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If(Local0 == 0 || Local0 == 1) {
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Local1 = 0x0f
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}
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ElseIf(LEqual(Local0, 2)) {
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Store(0x3, Local1)
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ElseIf(Local0 == 2) {
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Local1 = 3
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}
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ElseIf(LEqual(Local0, 3)) {
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Store(Zero, Local1)
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ElseIf(Local0 == 3) {
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Local1 = 0
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}
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And(RPM3, 0xFFFFFFF0, Local0)
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Or(Local0, Local1, RPM3)
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And(PRM2, 0xFFFFFFF0, Local0)
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Or(Local0, Local1, PRM2)
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And(SSEN, 0xFFFFFFF0, Local0)
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Or(Local0, Local1, SSEN)
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And(X2PR, 0xFFFFFFF0, Local0)
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Or(Local0, Local1, X2PR)
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Local0 = RPM3 & 0xfffffff0
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RPM3 = Local0 | Local1
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Local0 = PRM2 & 0xfffffff0
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PRM2 = Local0 | Local1
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Local0 = SSEN & 0xfffffff0
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SSEN = Local0 | Local1
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Local0 = X2PR & 0xfffffff0
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X2PR = Local0 | Local1
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}
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Return(Arg1)
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}
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