diff --git a/src/cpu/amd/agesa/family10/Kconfig b/src/cpu/amd/agesa/family10/Kconfig index 81070e5534..abaa898b38 100755 --- a/src/cpu/amd/agesa/family10/Kconfig +++ b/src/cpu/amd/agesa/family10/Kconfig @@ -40,10 +40,6 @@ config CDB hex default 0x18 -config XIP_ROM_BASE - hex - default 0xfff80000 - config XIP_ROM_SIZE hex default 0x80000 diff --git a/src/cpu/amd/agesa/family12/Kconfig b/src/cpu/amd/agesa/family12/Kconfig index 5679396f18..c53ee57409 100755 --- a/src/cpu/amd/agesa/family12/Kconfig +++ b/src/cpu/amd/agesa/family12/Kconfig @@ -57,11 +57,6 @@ config CDB default 0x18 depends on CPU_AMD_AGESA_FAMILY12 -config XIP_ROM_BASE - hex - default 0xfff80000 - depends on CPU_AMD_AGESA_FAMILY12 - config XIP_ROM_SIZE hex default 0x80000 diff --git a/src/cpu/amd/agesa/family14/Kconfig b/src/cpu/amd/agesa/family14/Kconfig index 8f3e766e6f..702270c1cc 100644 --- a/src/cpu/amd/agesa/family14/Kconfig +++ b/src/cpu/amd/agesa/family14/Kconfig @@ -57,11 +57,6 @@ config CDB default 0x18 depends on CPU_AMD_AGESA_FAMILY14 -config XIP_ROM_BASE - hex - default 0xfff80000 - depends on CPU_AMD_AGESA_FAMILY14 - config XIP_ROM_SIZE hex default 0x80000 diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc index b9e02f3b8f..955aec9514 100644 --- a/src/cpu/amd/car/cache_as_ram.inc +++ b/src/cpu/amd/car/cache_as_ram.inc @@ -279,7 +279,7 @@ clear_fixed_var_mtrr_out: movl $(((CONFIG_RAMTOP) + TOP_MEM_MASK) & ~TOP_MEM_MASK) , %eax wrmsr -#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE) +#if CONFIG_XIP_ROM_SIZE /* Enable write base caching so we can do execute in place (XIP) * on the flash ROM. @@ -302,7 +302,7 @@ clear_fixed_var_mtrr_out: wbcache_post_fam10_setup: movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax wrmsr -#endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */ +#endif /* CONFIG_XIP_ROM_SIZE */ /* Set the default memory type and enable fixed and variable MTRRs. */ movl $MTRRdefType_MSR, %ecx diff --git a/src/cpu/amd/socket_AM2r2/Kconfig b/src/cpu/amd/socket_AM2r2/Kconfig index c7cff14c04..ae4d45866d 100644 --- a/src/cpu/amd/socket_AM2r2/Kconfig +++ b/src/cpu/amd/socket_AM2r2/Kconfig @@ -30,11 +30,6 @@ config CDB default 0x18 depends on CPU_AMD_SOCKET_AM2R2 -config XIP_ROM_BASE - hex - default 0xfff80000 - depends on CPU_AMD_SOCKET_AM2R2 - config XIP_ROM_SIZE hex default 0x80000 diff --git a/src/cpu/amd/socket_AM3/Kconfig b/src/cpu/amd/socket_AM3/Kconfig index c718eadba6..ed656f13b2 100644 --- a/src/cpu/amd/socket_AM3/Kconfig +++ b/src/cpu/amd/socket_AM3/Kconfig @@ -30,11 +30,6 @@ config CDB default 0x18 depends on CPU_AMD_SOCKET_AM3 -config XIP_ROM_BASE - hex - default 0xfff80000 - depends on CPU_AMD_SOCKET_AM3 - config XIP_ROM_SIZE hex default 0x80000 diff --git a/src/cpu/amd/socket_ASB2/Kconfig b/src/cpu/amd/socket_ASB2/Kconfig index 964a59f706..7784a8d4df 100644 --- a/src/cpu/amd/socket_ASB2/Kconfig +++ b/src/cpu/amd/socket_ASB2/Kconfig @@ -30,11 +30,6 @@ config CDB default 0x18 depends on CPU_AMD_SOCKET_ASB2 -config XIP_ROM_BASE - hex - default 0xfff80000 - depends on CPU_AMD_SOCKET_ASB2 - config XIP_ROM_SIZE hex default 0x80000 diff --git a/src/cpu/amd/socket_C32/Kconfig b/src/cpu/amd/socket_C32/Kconfig index 7ffa374962..56324dc776 100644 --- a/src/cpu/amd/socket_C32/Kconfig +++ b/src/cpu/amd/socket_C32/Kconfig @@ -30,11 +30,6 @@ config CDB default 0x18 depends on CPU_AMD_SOCKET_C32 -config XIP_ROM_BASE - hex - default 0xfff80000 - depends on CPU_AMD_SOCKET_C32 - config XIP_ROM_SIZE hex default 0x80000 diff --git a/src/cpu/amd/socket_F_1207/Kconfig b/src/cpu/amd/socket_F_1207/Kconfig index 224059a1a1..df9856661c 100644 --- a/src/cpu/amd/socket_F_1207/Kconfig +++ b/src/cpu/amd/socket_F_1207/Kconfig @@ -29,11 +29,6 @@ config CDB default 0x18 depends on CPU_AMD_SOCKET_F_1207 -config XIP_ROM_BASE - hex - default 0xfff80000 - depends on CPU_AMD_SOCKET_F_1207 - config XIP_ROM_SIZE hex default 0x80000 diff --git a/src/cpu/intel/car/cache_as_ram.inc b/src/cpu/intel/car/cache_as_ram.inc index 26fec6e594..7742a68225 100644 --- a/src/cpu/intel/car/cache_as_ram.inc +++ b/src/cpu/intel/car/cache_as_ram.inc @@ -229,7 +229,7 @@ clear_fixed_var_mtrr_out: simplemask CacheSize, 0 wrmsr -#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE) +#if CONFIG_XIP_ROM_SIZE /* * Enable write base caching so we can do execute in place (XIP) @@ -250,7 +250,7 @@ clear_fixed_var_mtrr_out: movl $0x0000000f, %edx movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax wrmsr -#endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */ +#endif /* CONFIG_XIP_ROM_SIZE */ /* Enable cache. */ movl %cr0, %eax diff --git a/src/cpu/intel/model_106cx/cache_as_ram.inc b/src/cpu/intel/model_106cx/cache_as_ram.inc index 9f7ceaf247..eb3d650ed2 100644 --- a/src/cpu/intel/model_106cx/cache_as_ram.inc +++ b/src/cpu/intel/model_106cx/cache_as_ram.inc @@ -98,7 +98,7 @@ clear_mtrrs: orl $(1 << 30), %eax movl %eax, %cr0 -#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE) +#if CONFIG_XIP_ROM_SIZE /* Enable cache for our code in Flash because we do XIP here */ movl $MTRRphysBase_MSR(1), %ecx xorl %edx, %edx @@ -115,7 +115,7 @@ clear_mtrrs: xorl %edx, %edx movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax wrmsr -#endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */ +#endif /* CONFIG_XIP_ROM_SIZE */ /* Enable cache. */ movl %cr0, %eax diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc index 3a12cf6dd3..18ada2965b 100644 --- a/src/cpu/intel/model_6ex/cache_as_ram.inc +++ b/src/cpu/intel/model_6ex/cache_as_ram.inc @@ -98,7 +98,7 @@ clear_mtrrs: orl $(1 << 30), %eax movl %eax, %cr0 -#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE) +#if CONFIG_XIP_ROM_SIZE /* Enable cache for our code in Flash because we do XIP here */ movl $MTRRphysBase_MSR(1), %ecx xorl %edx, %edx @@ -115,7 +115,7 @@ clear_mtrrs: movl $0x0000000f, %edx movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax wrmsr -#endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */ +#endif /* CONFIG_XIP_ROM_SIZE */ /* Enable cache. */ movl %cr0, %eax diff --git a/src/cpu/intel/model_6fx/cache_as_ram.inc b/src/cpu/intel/model_6fx/cache_as_ram.inc index 2ba187271e..dfc4f3b2b9 100644 --- a/src/cpu/intel/model_6fx/cache_as_ram.inc +++ b/src/cpu/intel/model_6fx/cache_as_ram.inc @@ -105,7 +105,7 @@ clear_mtrrs: orl $(1 << 30), %eax movl %eax, %cr0 -#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE) +#if CONFIG_XIP_ROM_SIZE /* Enable cache for our code in Flash because we do XIP here */ movl $MTRRphysBase_MSR(1), %ecx xorl %edx, %edx @@ -122,7 +122,7 @@ clear_mtrrs: movl $0x0000000f, %edx movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax wrmsr -#endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */ +#endif /* CONFIG_XIP_ROM_SIZE */ /* Enable cache. */ movl %cr0, %eax diff --git a/src/cpu/via/car/cache_as_ram.inc b/src/cpu/via/car/cache_as_ram.inc index ad2805ea2a..aad23690fd 100644 --- a/src/cpu/via/car/cache_as_ram.inc +++ b/src/cpu/via/car/cache_as_ram.inc @@ -240,7 +240,7 @@ testok: movl $(~(CONFIG_RAMTOP - CONFIG_RAMBASE - 1) | MTRRphysMaskValid), %eax wrmsr - /* Cache XIP_ROM_BASE-SIZE to speedup coreboot code. */ + /* Cache XIP_ROM area to speedup coreboot code. */ movl $MTRRphysBase_MSR(1), %ecx xorl %edx, %edx /* diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index eed7d8f26f..348f0ef92d 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -27,10 +27,6 @@ config TSC_CALIBRATE_WITH_IO bool default n -config XIP_ROM_BASE - hex - default 0xffff0000 - config XIP_ROM_SIZE hex default 0x10000 diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index dc238e7a51..c3b3e222f9 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -45,23 +45,13 @@ void set_var_mtrr_resource(void *gp, struct device *dev, struct resource *res); void x86_setup_fixed_mtrrs(void); #endif -/* Validate CONFIG_XIP_ROM_SIZE and CONFIG_XIP_ROM_BASE */ -#if defined(CONFIG_XIP_ROM_SIZE) && !defined(CONFIG_XIP_ROM_BASE) -# error "CONFIG_XIP_ROM_SIZE without CONFIG_XIP_ROM_BASE" -#endif -#if defined(CONFIG_XIP_ROM_BASE) && !defined(CONFIG_XIP_ROM_SIZE) -# error "CONFIG_XIP_ROM_BASE without CONFIG_XIP_ROM_SIZE" -#endif #if !defined(CONFIG_RAMTOP) # error "CONFIG_RAMTOP not defined" #endif -#if defined(CONFIG_XIP_ROM_SIZE) && ((CONFIG_XIP_ROM_SIZE & (CONFIG_XIP_ROM_SIZE -1)) != 0) +#if ((CONFIG_XIP_ROM_SIZE & (CONFIG_XIP_ROM_SIZE -1)) != 0) # error "CONFIG_XIP_ROM_SIZE is not a power of 2" #endif -#if defined(CONFIG_XIP_ROM_SIZE) && ((CONFIG_XIP_ROM_BASE % CONFIG_XIP_ROM_SIZE) != 0) -# error "CONFIG_XIP_ROM_BASE is not a multiple of CONFIG_XIP_ROM_SIZE" -#endif #if (CONFIG_RAMTOP & (CONFIG_RAMTOP - 1)) != 0 # error "CONFIG_RAMTOP must be a power of 2" diff --git a/src/mainboard/supermicro/h8dmr_fam10/README b/src/mainboard/supermicro/h8dmr_fam10/README index 040c24498c..485e7c852c 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/README +++ b/src/mainboard/supermicro/h8dmr_fam10/README @@ -21,8 +21,3 @@ See also this thread: http://www.coreboot.org/pipermail/coreboot/2009-September/ Ward, 2009-09-22 -mansoor@iwavesystems.com said, about the last issue: - - Try enabling CONFIG_XIP_ROM_BASE. It solved the same problem for me in my board. - -So, that's a todo.