soc/intel/apollolake: Change PCI macros to match Skylake
Change PCI macros in such a way they can be transparently used across romstage and ramstage. Change-Id: Idc708c1990f2fc1d941bb82efcb0a697524f2eca Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15483 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
Andrey Petrov
Duncan Laurie
parent
9d8b2ffb49
commit
78461a9d55
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@ -134,49 +134,49 @@ static void disable_dev(struct device *dev, struct FSP_S_CONFIG *silconfig) {
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case XDCI_DEVFN:
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silconfig->UsbOtg = 0;
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break;
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case I2C0_DEVFN:
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case LPSS_DEVFN_I2C0:
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silconfig->I2c0Enable = 0;
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break;
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case I2C1_DEVFN:
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case LPSS_DEVFN_I2C1:
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silconfig->I2c1Enable = 0;
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break;
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case I2C2_DEVFN:
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case LPSS_DEVFN_I2C2:
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silconfig->I2c2Enable = 0;
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break;
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case I2C3_DEVFN:
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case LPSS_DEVFN_I2C3:
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silconfig->I2c3Enable = 0;
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break;
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case I2C4_DEVFN:
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case LPSS_DEVFN_I2C4:
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silconfig->I2c4Enable = 0;
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break;
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case I2C5_DEVFN:
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case LPSS_DEVFN_I2C5:
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silconfig->I2c5Enable = 0;
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break;
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case I2C6_DEVFN:
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case LPSS_DEVFN_I2C6:
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silconfig->I2c6Enable = 0;
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break;
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case I2C7_DEVFN:
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case LPSS_DEVFN_I2C7:
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silconfig->I2c7Enable = 0;
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break;
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case UART0_DEVFN:
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case LPSS_DEVFN_UART0:
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silconfig->Hsuart0Enable = 0;
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break;
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case UART1_DEVFN:
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case LPSS_DEVFN_UART1:
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silconfig->Hsuart1Enable = 0;
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break;
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case UART2_DEVFN:
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case LPSS_DEVFN_UART2:
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silconfig->Hsuart2Enable = 0;
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break;
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case UART3_DEVFN:
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case LPSS_DEVFN_UART3:
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silconfig->Hsuart3Enable = 0;
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break;
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case SPI0_DEVFN:
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case LPSS_DEVFN_SPI0:
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silconfig->Spi0Enable = 0;
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break;
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case SPI1_DEVFN:
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case LPSS_DEVFN_SPI1:
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silconfig->Spi1Enable = 0;
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break;
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case SPI2_DEVFN:
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case LPSS_DEVFN_SPI2:
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silconfig->Spi2Enable = 0;
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break;
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case SDCARD_DEVFN:
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@ -201,7 +201,7 @@ static void disable_dev(struct device *dev, struct FSP_S_CONFIG *silconfig) {
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static void parse_devicetree(struct FSP_S_CONFIG *silconfig)
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{
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struct device *dev = dev_find_slot(0, NB_DEVFN);
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struct device *dev = NB_DEV_ROOT;
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if (!dev) {
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printk(BIOS_ERR, "Could not find root device\n");
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@ -222,7 +222,8 @@ void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *silupd)
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/* Load VBT before devicetree-specific config. */
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silconfig->GraphicsConfigPtr = (uintptr_t)vbt;
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struct device *dev = dev_find_slot(NB_BUS, NB_DEVFN);
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struct device *dev = NB_DEV_ROOT;
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if (!dev || !dev->chip_info) {
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printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n");
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return;
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@ -17,63 +17,87 @@
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#include <rules.h>
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#define _LPSS_PCI_DEVFN(slot, func) PCI_DEVFN(LPSS_DEV_SLOT_##slot, func)
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#define _LPSS_PCI_DEVFN(slot, func) PCI_DEVFN(LPSS_DEV_SLOT_##slot, func)
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#define _PCI_DEVFN(slot, func) PCI_DEVFN(slot, func)
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#if !defined(__SIMPLE_DEVICE__)
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#include <device/device.h>
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#include <device/pci_def.h>
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#define _LPSS_PCI_DEV(slot, func) dev_find_slot(0, _LPSS_PCI_DEVFN(slot, func))
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#define _LPSS_PCI_DEV(slot, func) dev_find_slot(0, _LPSS_PCI_DEVFN(slot, func))
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#define _PCI_DEV(slot, func) dev_find_slot(0, PCI_DEVFN(slot, func))
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#else
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#include <arch/io.h>
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#define _LPSS_PCI_DEV(slot, func) PCI_DEV(0, LPSS_DEV_SLOT_##slot, func)
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#define _LPSS_PCI_DEV(slot, func) PCI_DEV(0, LPSS_DEV_SLOT_##slot, func)
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#define _PCI_DEV(slot, func) PCI_DEV(0, slot, func)
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#endif
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#define NB_DEVFN _PCI_DEVFN(0, 0)
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#define NB_DEV_ROOT _PCI_DEV(0x0, 0)
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#define P2SB_DEV _PCI_DEV(0xd, 0)
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#define PMC_DEV _PCI_DEV(0xd, 1)
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#define SPI_DEV _PCI_DEV(0xd, 2)
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#define ISH_DEV _PCI_DEV(0x11, 0)
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#define ISH_DEVFN _PCI_DEVFN(0x11, 0)
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#define SATA_DEV _PCI_DEV(0x12, 0)
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#define SATA_DEVFN _PCI_DEVFN(0x12, 0)
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#define PCIEA0_DEVFN _PCI_DEVFN(0x13, 0)
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#define PCIEA1_DEVFN _PCI_DEVFN(0x13, 1)
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#define PCIEA2_DEVFN _PCI_DEVFN(0x13, 2)
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#define PCIEA3_DEVFN _PCI_DEVFN(0x13, 3)
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#define PCIEB0_DEVFN _PCI_DEVFN(0x14, 0)
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#define PCIEB1_DEVFN _PCI_DEVFN(0x14, 1)
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#define XHCI_DEV _PCI_DEV(0x15, 0)
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#define XHCI_DEVFN _PCI_DEVFN(0x15, 0)
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#define XDCI_DEV _PCI_DEV(0x15, 1)
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#define XDCI_DEVFN _PCI_DEVFN(0x15, 1)
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/* LPSS I2C, 2 devices cover 8 controllers */
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#define LPSS_DEV_SLOT_I2C_D0 0x16
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#define LPSS_DEVFN_I2C0 _LPSS_PCI_DEVFN(I2C_D0, 0)
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#define LPSS_DEVFN_I2C1 _LPSS_PCI_DEVFN(I2C_D0, 1)
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#define LPSS_DEVFN_I2C2 _LPSS_PCI_DEVFN(I2C_D0, 2)
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#define LPSS_DEVFN_I2C3 _LPSS_PCI_DEVFN(I2C_D0, 3)
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#define LPSS_DEV_SLOT_I2C_D1 0x17
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#define LPSS_DEVFN_I2C4 _LPSS_PCI_DEVFN(I2C_D1, 0)
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#define LPSS_DEVFN_I2C5 _LPSS_PCI_DEVFN(I2C_D1, 1)
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#define LPSS_DEVFN_I2C6 _LPSS_PCI_DEVFN(I2C_D1, 2)
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#define LPSS_DEVFN_I2C7 _LPSS_PCI_DEVFN(I2C_D1, 3)
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/* LPSS UART */
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#define LPSS_DEV_SLOT_UART 0x18
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#define LPSS_DEVFN_UART0 _LPSS_PCI_DEVFN(UART, 0)
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#define LPSS_DEVFN_UART1 _LPSS_PCI_DEVFN(UART, 1)
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#define LPSS_DEVFN_UART2 _LPSS_PCI_DEVFN(UART, 2)
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#define LPSS_DEVFN_UART3 _LPSS_PCI_DEVFN(UART, 3)
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#define LPSS_DEV_UART0 _LPSS_PCI_DEV(UART, 0)
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#define LPSS_DEV_UART1 _LPSS_PCI_DEV(UART, 1)
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#define LPSS_DEV_UART2 _LPSS_PCI_DEV(UART, 2)
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#define LPSS_DEV_UART3 _LPSS_PCI_DEV(UART, 3)
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#define LPSS_DEV_SLOT_UART 0x18
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#define LPSS_DEVFN_UART0 _LPSS_PCI_DEVFN(UART, 0)
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#define LPSS_DEVFN_UART1 _LPSS_PCI_DEVFN(UART, 1)
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#define LPSS_DEVFN_UART2 _LPSS_PCI_DEVFN(UART, 2)
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#define LPSS_DEVFN_UART3 _LPSS_PCI_DEVFN(UART, 3)
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#define LPSS_DEV_UART0 _LPSS_PCI_DEV(UART, 0)
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#define LPSS_DEV_UART1 _LPSS_PCI_DEV(UART, 1)
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#define LPSS_DEV_UART2 _LPSS_PCI_DEV(UART, 2)
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#define LPSS_DEV_UART3 _LPSS_PCI_DEV(UART, 3)
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#define NB_BUS 0
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#define NB_DEVFN PCI_DEVFN(0, 0)
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#define NB_DEV_ROOT PCI_DEV(NB_BUS, 0x0, 0)
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#define P2SB_DEV PCI_DEV(0, 0xd, 0)
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#define PMC_DEV PCI_DEV(0, 0xd, 1)
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#define SPI_DEV PCI_DEV(0, 0xd, 2)
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#define LPC_DEV PCI_DEV(0, 0x1f, 0)
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/* LPSS SPI */
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#define LPSS_DEV_SLOT_SPI 0x19
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#define LPSS_DEVFN_SPI0 _LPSS_PCI_DEVFN(SPI, 0)
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#define LPSS_DEVFN_SPI1 _LPSS_PCI_DEVFN(SPI, 1)
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#define LPSS_DEVFN_SPI2 _LPSS_PCI_DEVFN(SPI, 2)
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#define ISH_DEVFN PCI_DEVFN(0x11, 0)
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#define SATA_DEVFN PCI_DEVFN(0x12, 0)
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#define PCIEA0_DEVFN PCI_DEVFN(0x13, 0)
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#define PCIEA1_DEVFN PCI_DEVFN(0x13, 1)
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#define PCIEA2_DEVFN PCI_DEVFN(0x13, 2)
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#define PCIEA3_DEVFN PCI_DEVFN(0x13, 3)
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#define PCIEB0_DEVFN PCI_DEVFN(0x14, 0)
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#define PCIEB1_DEVFN PCI_DEVFN(0x14, 1)
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#define XHCI_DEVFN PCI_DEVFN(0x15, 0)
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#define XDCI_DEVFN PCI_DEVFN(0x15, 1)
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#define I2C0_DEVFN PCI_DEVFN(0x16, 0)
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#define I2C1_DEVFN PCI_DEVFN(0x16, 1)
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#define I2C2_DEVFN PCI_DEVFN(0x16, 2)
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#define I2C3_DEVFN PCI_DEVFN(0x16, 3)
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#define I2C4_DEVFN PCI_DEVFN(0x17, 0)
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#define I2C5_DEVFN PCI_DEVFN(0x17, 1)
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#define I2C6_DEVFN PCI_DEVFN(0x17, 2)
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#define I2C7_DEVFN PCI_DEVFN(0x17, 3)
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#define UART0_DEVFN PCI_DEVFN(0x18, 0)
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#define UART1_DEVFN PCI_DEVFN(0x18, 1)
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#define UART2_DEVFN PCI_DEVFN(0x18, 2)
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#define UART3_DEVFN PCI_DEVFN(0x18, 3)
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#define SPI0_DEVFN PCI_DEVFN(0x19, 0)
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#define SPI1_DEVFN PCI_DEVFN(0x19, 1)
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#define SPI2_DEVFN PCI_DEVFN(0x19, 2)
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#define SDCARD_DEVFN PCI_DEVFN(0x1b, 0)
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#define EMMC_DEVFN PCI_DEVFN(0x1c, 0)
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#define SDIO_DEVFN PCI_DEVFN(0x1e, 0)
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#define SMBUS_DEVFN PCI_DEVFN(0x1f, 1)
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#define SDCARD_DEV _PCI_DEV(0x1b, 0)
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#define SDCARD_DEVFN _PCI_DEVFN(0x1b, 0)
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#define EMMC_DEV _PCI_DEV(0x1c, 0)
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#define EMMC_DEVFN _PCI_DEVFN(0x1c, 0)
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#define SDIO_DEV _PCI_DEV(0x1e, 0)
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#define SDIO_DEVFN _PCI_DEVFN(0x1e, 0)
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#define LPC_DEV _PCI_DEV(0x1f, 0)
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#define LPC_DEVFN _PCI_DEVFN(0x1f, 0)
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#define SMBUS_DEV _PCI_DEV(0x1f, 1)
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#define SMBUS_DEVFN _PCI_DEVFN(0x1f, 1)
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#endif
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