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soc/intel: Move soc_pch_pirq_init() to common code 

List of changes:
1. Rename soc_pch_pirq_init() as pch_pirq_init() and
move into common block code.
2. Remove redundant LPC functions from SoC directory and
refer from block/lpc directory.

TEST=Able to build and boot hatch and tglrvp platform without seeing
any functional impact.

Change-Id: I856b5ca024e58fd14b4d1721f23d9516a283ebf8
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45809
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Subrata Banik 2020-09-29 14:28:09 +05:30
parent 1366e4438d
commit 78463a7d26
10 changed files with 79 additions and 418 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/soc/intel/cannonlake/acpi/pci_irqs.asl
View File

@ -76,7 +76,7 @@ Name (PICP, Package () {
Name (PICN, Package () { Name (PICN, Package () {
/* /*
* If the setting change in soc_pch_pirq_init(), then * If the setting change in pch_pirq_init(), then
* please make the same static IRQ changes here as well. * please make the same static IRQ changes here as well.
*/ */
/* D31: cAVS, SMBus, GbE, Nothpeak */ /* D31: cAVS, SMBus, GbE, Nothpeak */

70
src/soc/intel/cannonlake/lpc.c
View File

@ -90,74 +90,6 @@ static void soc_mirror_dmi_pcr_io_dec(void)
soc_setup_dmi_pcr_io_dec(&io_dec_arr[0]); soc_setup_dmi_pcr_io_dec(&io_dec_arr[0]);
} }
/*
* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control
* 0x00 - 0000 = Reserved
* 0x01 - 0001 = Reserved
* 0x02 - 0010 = Reserved
* 0x03 - 0011 = IRQ3
* 0x04 - 0100 = IRQ4
* 0x05 - 0101 = IRQ5
* 0x06 - 0110 = IRQ6
* 0x07 - 0111 = IRQ7
* 0x08 - 1000 = Reserved
* 0x09 - 1001 = IRQ9
* 0x0A - 1010 = IRQ10
* 0x0B - 1011 = IRQ11
* 0x0C - 1100 = IRQ12
* 0x0D - 1101 = Reserved
* 0x0E - 1110 = IRQ14
* 0x0F - 1111 = IRQ15
* PIRQ[n]_ROUT[7] - PIRQ Routing Control
* 0x80 - The PIRQ is not routed.
*/
void soc_pch_pirq_init(const struct device *dev)
{
struct device *irq_dev;
uint8_t pch_interrupt_routing[MAX_PXRC_CONFIG];
pch_interrupt_routing[0] = PCH_IRQ11;
pch_interrupt_routing[1] = PCH_IRQ10;
pch_interrupt_routing[2] = PCH_IRQ11;
pch_interrupt_routing[3] = PCH_IRQ11;
pch_interrupt_routing[4] = PCH_IRQ11;
pch_interrupt_routing[5] = PCH_IRQ11;
pch_interrupt_routing[6] = PCH_IRQ11;
pch_interrupt_routing[7] = PCH_IRQ11;
itss_irq_init(pch_interrupt_routing);
for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
u8 int_pin = 0, int_line = 0;
if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI)
continue;
int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN);
switch (int_pin) {
case 1: /* INTA# */
int_line = PCH_IRQ11;
break;
case 2: /* INTB# */
int_line = PCH_IRQ10;
break;
case 3: /* INTC# */
int_line = PCH_IRQ11;
break;
case 4: /* INTD# */
int_line = PCH_IRQ11;
break;
}
if (!int_line)
continue;
pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line);
}
}
static void pch_misc_init(void) static void pch_misc_init(void)
{ {
uint8_t reg8; uint8_t reg8;
@ -186,7 +118,7 @@ void lpc_soc_init(struct device *dev)
/* Interrupt configuration */ /* Interrupt configuration */
pch_enable_ioapic(); pch_enable_ioapic();
soc_pch_pirq_init(dev); pch_pirq_init();
setup_i8259(); setup_i8259();
i8259_configure_irq_trigger(9, 1); i8259_configure_irq_trigger(9, 1);
soc_mirror_dmi_pcr_io_dec(); soc_mirror_dmi_pcr_io_dec();

4
src/soc/intel/common/block/include/intelblocks/lpc_lib.h
View File

@ -97,8 +97,6 @@ void lpc_disable_clkrun(void);
void lpc_io_setup_comm_a_b(void); void lpc_io_setup_comm_a_b(void);
/* Enable PCH LPC by setting up generic decode range registers. */ /* Enable PCH LPC by setting up generic decode range registers. */
void pch_enable_lpc(void); void pch_enable_lpc(void);
/* Retrieve and setup SoC specific PCH LPC interrupt routing. */
void soc_pch_pirq_init(const struct device *dev);
/* Get SoC's generic IO decoder range register settings. */ /* Get SoC's generic IO decoder range register settings. */
void soc_get_gen_io_dec_range(const struct device *dev, void soc_get_gen_io_dec_range(const struct device *dev,
uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES]); uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES]);
@ -109,5 +107,7 @@ void pch_lpc_add_new_resource(struct device *dev, uint8_t offset,
uintptr_t base, size_t size, unsigned long flags); uintptr_t base, size_t size, unsigned long flags);
/* Enable PCH IOAPIC */ /* Enable PCH IOAPIC */
void pch_enable_ioapic(void); void pch_enable_ioapic(void);
/* Retrieve and setup PCH LPC interrupt routing. */
void pch_pirq_init(void);
#endif /* _SOC_COMMON_BLOCK_LPC_LIB_H_ */ #endif /* _SOC_COMMON_BLOCK_LPC_LIB_H_ */

71
src/soc/intel/common/block/lpc/lpc_lib.c
View File

@ -7,9 +7,11 @@
#include <console/console.h> #include <console/console.h>
#include <device/pci.h> #include <device/pci.h>
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <intelblocks/itss.h>
#include <intelblocks/lpc_lib.h> #include <intelblocks/lpc_lib.h>
#include <lib.h> #include <lib.h>
#include "lpc_def.h" #include "lpc_def.h"
#include <soc/irq.h>
#include <soc/pci_devs.h> #include <soc/pci_devs.h>
uint16_t lpc_enable_fixed_io_ranges(uint16_t io_enables) uint16_t lpc_enable_fixed_io_ranges(uint16_t io_enables)
@ -280,7 +282,7 @@ void pch_enable_lpc(void)
lpc_set_gen_decode_range(gen_io_dec); lpc_set_gen_decode_range(gen_io_dec);
soc_setup_dmi_pcr_io_dec(gen_io_dec); soc_setup_dmi_pcr_io_dec(gen_io_dec);
if (ENV_PAYLOAD_LOADER) if (ENV_PAYLOAD_LOADER)
soc_pch_pirq_init(dev); pch_pirq_init();
} }
void lpc_enable_pci_clk_cntl(void) void lpc_enable_pci_clk_cntl(void)
@ -317,3 +319,70 @@ void pch_enable_ioapic(void)
*/ */
io_apic_write((void *)IO_APIC_ADDR, 0x03, 0x01); io_apic_write((void *)IO_APIC_ADDR, 0x03, 0x01);
} }
/*
* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control
* 0x00 - 0000 = Reserved
* 0x01 - 0001 = Reserved
* 0x02 - 0010 = Reserved
* 0x03 - 0011 = IRQ3
* 0x04 - 0100 = IRQ4
* 0x05 - 0101 = IRQ5
* 0x06 - 0110 = IRQ6
* 0x07 - 0111 = IRQ7
* 0x08 - 1000 = Reserved
* 0x09 - 1001 = IRQ9
* 0x0A - 1010 = IRQ10
* 0x0B - 1011 = IRQ11
* 0x0C - 1100 = IRQ12
* 0x0D - 1101 = Reserved
* 0x0E - 1110 = IRQ14
* 0x0F - 1111 = IRQ15
* PIRQ[n]_ROUT[7] - PIRQ Routing Control
* 0x80 - The PIRQ is not routed.
*/
void pch_pirq_init(void)
{
const struct device *irq_dev;
uint8_t pch_interrupt_routing[MAX_PXRC_CONFIG];
pch_interrupt_routing[0] = PCH_IRQ11;
pch_interrupt_routing[1] = PCH_IRQ10;
pch_interrupt_routing[2] = PCH_IRQ11;
pch_interrupt_routing[3] = PCH_IRQ11;
pch_interrupt_routing[4] = PCH_IRQ11;
pch_interrupt_routing[5] = PCH_IRQ11;
pch_interrupt_routing[6] = PCH_IRQ11;
pch_interrupt_routing[7] = PCH_IRQ11;
itss_irq_init(pch_interrupt_routing);
for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
uint8_t int_pin = 0, int_line = 0;
if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI)
continue;
int_pin = pci_read_config8(PCI_BDF(irq_dev), PCI_INTERRUPT_PIN);
switch (int_pin) {
case 1: /* INTA# */
int_line = PCH_IRQ11;
break;
case 2: /* INTB# */
int_line = PCH_IRQ10;
break;
case 3: /* INTC# */
int_line = PCH_IRQ11;
break;
case 4: /* INTD# */
int_line = PCH_IRQ11;
break;
}
if (!int_line)
continue;
pci_write_config8(PCI_BDF(irq_dev), PCI_INTERRUPT_LINE, int_line);
}
}

70
src/soc/intel/elkhartlake/espi.c
View File

@ -64,74 +64,6 @@ static void soc_mirror_dmi_pcr_io_dec(void)
soc_setup_dmi_pcr_io_dec(&io_dec_arr[0]); soc_setup_dmi_pcr_io_dec(&io_dec_arr[0]);
} }
/*
* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control
* 0x00 - 0000 = Reserved
* 0x01 - 0001 = Reserved
* 0x02 - 0010 = Reserved
* 0x03 - 0011 = IRQ3
* 0x04 - 0100 = IRQ4
* 0x05 - 0101 = IRQ5
* 0x06 - 0110 = IRQ6
* 0x07 - 0111 = IRQ7
* 0x08 - 1000 = Reserved
* 0x09 - 1001 = IRQ9
* 0x0A - 1010 = IRQ10
* 0x0B - 1011 = IRQ11
* 0x0C - 1100 = IRQ12
* 0x0D - 1101 = Reserved
* 0x0E - 1110 = IRQ14
* 0x0F - 1111 = IRQ15
* PIRQ[n]_ROUT[7] - PIRQ Routing Control
* 0x80 - The PIRQ is not routed.
*/
void soc_pch_pirq_init(const struct device *dev)
{
struct device *irq_dev;
uint8_t pch_interrupt_routing[MAX_PXRC_CONFIG];
pch_interrupt_routing[0] = PCH_IRQ11;
pch_interrupt_routing[1] = PCH_IRQ10;
pch_interrupt_routing[2] = PCH_IRQ11;
pch_interrupt_routing[3] = PCH_IRQ11;
pch_interrupt_routing[4] = PCH_IRQ11;
pch_interrupt_routing[5] = PCH_IRQ11;
pch_interrupt_routing[6] = PCH_IRQ11;
pch_interrupt_routing[7] = PCH_IRQ11;
itss_irq_init(pch_interrupt_routing);
for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
uint8_t int_pin = 0, int_line = 0;
if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI)
continue;
int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN);
switch (int_pin) {
case 1: /* INTA# */
int_line = PCH_IRQ11;
break;
case 2: /* INTB# */
int_line = PCH_IRQ10;
break;
case 3: /* INTC# */
int_line = PCH_IRQ11;
break;
case 4: /* INTD# */
int_line = PCH_IRQ11;
break;
}
if (!int_line)
continue;
pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line);
}
}
static void pch_misc_init(void) static void pch_misc_init(void)
{ {
uint8_t reg8; uint8_t reg8;
@ -161,7 +93,7 @@ void lpc_soc_init(struct device *dev)
/* Interrupt configuration */ /* Interrupt configuration */
pch_enable_ioapic(); pch_enable_ioapic();
soc_pch_pirq_init(dev); pch_pirq_init();
setup_i8259(); setup_i8259();
i8259_configure_irq_trigger(9, 1); i8259_configure_irq_trigger(9, 1);
soc_mirror_dmi_pcr_io_dec(); soc_mirror_dmi_pcr_io_dec();

70
src/soc/intel/icelake/espi.c
View File

@ -83,74 +83,6 @@ static void soc_mirror_dmi_pcr_io_dec(void)
soc_setup_dmi_pcr_io_dec(&io_dec_arr[0]); soc_setup_dmi_pcr_io_dec(&io_dec_arr[0]);
} }
/*
* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control
* 0x00 - 0000 = Reserved
* 0x01 - 0001 = Reserved
* 0x02 - 0010 = Reserved
* 0x03 - 0011 = IRQ3
* 0x04 - 0100 = IRQ4
* 0x05 - 0101 = IRQ5
* 0x06 - 0110 = IRQ6
* 0x07 - 0111 = IRQ7
* 0x08 - 1000 = Reserved
* 0x09 - 1001 = IRQ9
* 0x0A - 1010 = IRQ10
* 0x0B - 1011 = IRQ11
* 0x0C - 1100 = IRQ12
* 0x0D - 1101 = Reserved
* 0x0E - 1110 = IRQ14
* 0x0F - 1111 = IRQ15
* PIRQ[n]_ROUT[7] - PIRQ Routing Control
* 0x80 - The PIRQ is not routed.
*/
void soc_pch_pirq_init(const struct device *dev)
{
struct device *irq_dev;
uint8_t pch_interrupt_routing[MAX_PXRC_CONFIG];
pch_interrupt_routing[0] = PCH_IRQ11;
pch_interrupt_routing[1] = PCH_IRQ10;
pch_interrupt_routing[2] = PCH_IRQ11;
pch_interrupt_routing[3] = PCH_IRQ11;
pch_interrupt_routing[4] = PCH_IRQ11;
pch_interrupt_routing[5] = PCH_IRQ11;
pch_interrupt_routing[6] = PCH_IRQ11;
pch_interrupt_routing[7] = PCH_IRQ11;
itss_irq_init(pch_interrupt_routing);
for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
u8 int_pin = 0, int_line = 0;
if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI)
continue;
int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN);
switch (int_pin) {
case 1: /* INTA# */
int_line = PCH_IRQ11;
break;
case 2: /* INTB# */
int_line = PCH_IRQ10;
break;
case 3: /* INTC# */
int_line = PCH_IRQ11;
break;
case 4: /* INTD# */
int_line = PCH_IRQ11;
break;
}
if (!int_line)
continue;
pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line);
}
}
static void pch_misc_init(void) static void pch_misc_init(void)
{ {
uint8_t reg8; uint8_t reg8;
@ -180,7 +112,7 @@ void lpc_soc_init(struct device *dev)
/* Interrupt configuration */ /* Interrupt configuration */
pch_enable_ioapic(); pch_enable_ioapic();
soc_pch_pirq_init(dev); pch_pirq_init();
setup_i8259(); setup_i8259();
i8259_configure_irq_trigger(9, 1); i8259_configure_irq_trigger(9, 1);
soc_mirror_dmi_pcr_io_dec(); soc_mirror_dmi_pcr_io_dec();

70
src/soc/intel/jasperlake/espi.c
View File

@ -65,74 +65,6 @@ static void soc_mirror_dmi_pcr_io_dec(void)
soc_setup_dmi_pcr_io_dec(&io_dec_arr[0]); soc_setup_dmi_pcr_io_dec(&io_dec_arr[0]);
} }
/*
* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control
* 0x00 - 0000 = Reserved
* 0x01 - 0001 = Reserved
* 0x02 - 0010 = Reserved
* 0x03 - 0011 = IRQ3
* 0x04 - 0100 = IRQ4
* 0x05 - 0101 = IRQ5
* 0x06 - 0110 = IRQ6
* 0x07 - 0111 = IRQ7
* 0x08 - 1000 = Reserved
* 0x09 - 1001 = IRQ9
* 0x0A - 1010 = IRQ10
* 0x0B - 1011 = IRQ11
* 0x0C - 1100 = IRQ12
* 0x0D - 1101 = Reserved
* 0x0E - 1110 = IRQ14
* 0x0F - 1111 = IRQ15
* PIRQ[n]_ROUT[7] - PIRQ Routing Control
* 0x80 - The PIRQ is not routed.
*/
void soc_pch_pirq_init(const struct device *dev)
{
struct device *irq_dev;
uint8_t pch_interrupt_routing[MAX_PXRC_CONFIG];
pch_interrupt_routing[0] = PCH_IRQ11;
pch_interrupt_routing[1] = PCH_IRQ10;
pch_interrupt_routing[2] = PCH_IRQ11;
pch_interrupt_routing[3] = PCH_IRQ11;
pch_interrupt_routing[4] = PCH_IRQ11;
pch_interrupt_routing[5] = PCH_IRQ11;
pch_interrupt_routing[6] = PCH_IRQ11;
pch_interrupt_routing[7] = PCH_IRQ11;
itss_irq_init(pch_interrupt_routing);
for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
u8 int_pin = 0, int_line = 0;
if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI)
continue;
int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN);
switch (int_pin) {
case 1: /* INTA# */
int_line = PCH_IRQ11;
break;
case 2: /* INTB# */
int_line = PCH_IRQ10;
break;
case 3: /* INTC# */
int_line = PCH_IRQ11;
break;
case 4: /* INTD# */
int_line = PCH_IRQ11;
break;
}
if (!int_line)
continue;
pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line);
}
}
static void pch_misc_init(void) static void pch_misc_init(void)
{ {
uint8_t reg8; uint8_t reg8;
@ -162,7 +94,7 @@ void lpc_soc_init(struct device *dev)
/* Interrupt configuration */ /* Interrupt configuration */
pch_enable_ioapic(); pch_enable_ioapic();
soc_pch_pirq_init(dev); pch_pirq_init();
setup_i8259(); setup_i8259();
i8259_configure_irq_trigger(9, 1); i8259_configure_irq_trigger(9, 1);
soc_mirror_dmi_pcr_io_dec(); soc_mirror_dmi_pcr_io_dec();

68
src/soc/intel/skylake/irq.c
View File

@ -215,71 +215,3 @@ void soc_irq_settings(FSP_SIL_UPD *params)
/* TCO Irq enable/disable */ /* TCO Irq enable/disable */
params->TcoIrqEnable = config->TcoIrqEnable; params->TcoIrqEnable = config->TcoIrqEnable;
} }
/*
* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control
* 0x00 - 0000 = Reserved
* 0x01 - 0001 = Reserved
* 0x02 - 0010 = Reserved
* 0x03 - 0011 = IRQ3
* 0x04 - 0100 = IRQ4
* 0x05 - 0101 = IRQ5
* 0x06 - 0110 = IRQ6
* 0x07 - 0111 = IRQ7
* 0x08 - 1000 = Reserved
* 0x09 - 1001 = IRQ9
* 0x0A - 1010 = IRQ10
* 0x0B - 1011 = IRQ11
* 0x0C - 1100 = IRQ12
* 0x0D - 1101 = Reserved
* 0x0E - 1110 = IRQ14
* 0x0F - 1111 = IRQ15
* PIRQ[n]_ROUT[7] - PIRQ Routing Control
* 0x80 - The PIRQ is not routed.
*/
void soc_pch_pirq_init(const struct device *dev)
{
uint8_t pch_interrupt_routing[MAX_PXRC_CONFIG];
struct device *irq_dev;
pch_interrupt_routing[0] = PCH_IRQ11;
pch_interrupt_routing[1] = PCH_IRQ10;
pch_interrupt_routing[2] = PCH_IRQ11;
pch_interrupt_routing[3] = PCH_IRQ11;
pch_interrupt_routing[4] = PCH_IRQ11;
pch_interrupt_routing[5] = PCH_IRQ11;
pch_interrupt_routing[6] = PCH_IRQ11;
pch_interrupt_routing[7] = PCH_IRQ11;
itss_irq_init(pch_interrupt_routing);
for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
u8 int_pin = 0, int_line = 0;
if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI)
continue;
int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN);
switch (int_pin) {
case 1: /* INTA# */
int_line = PCH_IRQ11;
break;
case 2: /* INTB# */
int_line = PCH_IRQ10;
break;
case 3: /* INTC# */
int_line = PCH_IRQ11;
break;
case 4: /* INTD# */
int_line = PCH_IRQ11;
break;
}
if (!int_line)
continue;
pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line);
}
}

2
src/soc/intel/skylake/lpc.c
View File

@ -74,7 +74,7 @@ void lpc_soc_init(struct device *dev)
/* Interrupt configuration */ /* Interrupt configuration */
pch_enable_ioapic(); pch_enable_ioapic();
soc_pch_pirq_init(dev); pch_pirq_init();
setup_i8259(); setup_i8259();
i8259_configure_irq_trigger(9, 1); i8259_configure_irq_trigger(9, 1);
} }

70
src/soc/intel/tigerlake/espi.c
View File

@ -71,74 +71,6 @@ static void soc_mirror_dmi_pcr_io_dec(void)
soc_setup_dmi_pcr_io_dec(&io_dec_arr[0]); soc_setup_dmi_pcr_io_dec(&io_dec_arr[0]);
} }
/*
* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control
* 0x00 - 0000 = Reserved
* 0x01 - 0001 = Reserved
* 0x02 - 0010 = Reserved
* 0x03 - 0011 = IRQ3
* 0x04 - 0100 = IRQ4
* 0x05 - 0101 = IRQ5
* 0x06 - 0110 = IRQ6
* 0x07 - 0111 = IRQ7
* 0x08 - 1000 = Reserved
* 0x09 - 1001 = IRQ9
* 0x0A - 1010 = IRQ10
* 0x0B - 1011 = IRQ11
* 0x0C - 1100 = IRQ12
* 0x0D - 1101 = Reserved
* 0x0E - 1110 = IRQ14
* 0x0F - 1111 = IRQ15
* PIRQ[n]_ROUT[7] - PIRQ Routing Control
* 0x80 - The PIRQ is not routed.
*/
void soc_pch_pirq_init(const struct device *dev)
{
struct device *irq_dev;
uint8_t pch_interrupt_routing[MAX_PXRC_CONFIG];
pch_interrupt_routing[0] = PCH_IRQ11;
pch_interrupt_routing[1] = PCH_IRQ10;
pch_interrupt_routing[2] = PCH_IRQ11;
pch_interrupt_routing[3] = PCH_IRQ11;
pch_interrupt_routing[4] = PCH_IRQ11;
pch_interrupt_routing[5] = PCH_IRQ11;
pch_interrupt_routing[6] = PCH_IRQ11;
pch_interrupt_routing[7] = PCH_IRQ11;
itss_irq_init(pch_interrupt_routing);
for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
u8 int_pin = 0, int_line = 0;
if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI)
continue;
int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN);
switch (int_pin) {
case 1: /* INTA# */
int_line = PCH_IRQ11;
break;
case 2: /* INTB# */
int_line = PCH_IRQ10;
break;
case 3: /* INTC# */
int_line = PCH_IRQ11;
break;
case 4: /* INTD# */
int_line = PCH_IRQ11;
break;
}
if (!int_line)
continue;
pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line);
}
}
static void pch_misc_init(void) static void pch_misc_init(void)
{ {
uint8_t reg8; uint8_t reg8;
@ -168,7 +100,7 @@ void lpc_soc_init(struct device *dev)
/* Interrupt configuration */ /* Interrupt configuration */
pch_enable_ioapic(); pch_enable_ioapic();
soc_pch_pirq_init(dev); pch_pirq_init();
setup_i8259(); setup_i8259();
i8259_configure_irq_trigger(9, 1); i8259_configure_irq_trigger(9, 1);
soc_mirror_dmi_pcr_io_dec(); soc_mirror_dmi_pcr_io_dec();