soc/intel/denverton_ns: Add function to clear PMCON status bits

This patch adds an SoC function to clear GEN_PMCON_A status bits to
align with other IA coreboot implementations.

Added `MS4V` macro for GEN_PMCON_A bit 18 as per EDS doc:558579.

Additionally, removed `PMC_` prefix from PMC configuration register
macros GEN_PMCON_A/B and ETR3.

Moved PMC PCI device macro from pmc.h to pci_devs.h and name PCH_PMC_DEV
to PCH_DEV_PMC. Also, adjust PCI macros under B0:D31:Fx based on
function numbers.

BUG=b:211954778
TEST=None.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I2690ccd387b40c0d89cf133117fd91914e1b71a4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61974
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>

src/soc/intel/denverton_ns/include/soc/pci_devs.h

@@ -138,13 +138,15 @@
 
 #define PCH_DEV_SLOT_LPC 0x1f
 #define PCH_DEVFN_LPC _PCH_DEVFN(LPC, 0)
+#define PCH_DEVFN_P2SB _PCH_DEVFN(LPC, 1)
 #define PCH_DEVFN_PMC _PCH_DEVFN(LPC, 2)
 #define PCH_DEVFN_SMBUS _PCH_DEVFN(LPC, 4)
 #define PCH_DEVFN_SPI _PCH_DEVFN(LPC, 5)
 #define PCH_DEV_LPC _PCH_DEV(LPC, 0)
-#define PCH_DEV_SPI _PCH_DEV(LPC, 5)
 #define PCH_DEV_P2SB _PCH_DEV(LPC, 1)
+#define PCH_DEV_PMC _PCH_DEV(LPC, 2)
 #define PCH_DEV_SMBUS _PCH_DEV(LPC, 4)
+#define PCH_DEV_SPI _PCH_DEV(LPC, 5)
 
 /* VT-d support value to match FSP settings */
 /* "PCH IOAPIC Config" */

src/soc/intel/denverton_ns/include/soc/pm.h

@@ -45,4 +45,7 @@ void enable_gpe(uint32_t mask);
 void disable_gpe(uint32_t mask);
 void disable_all_gpe(void);
 
+/* Clear PMCON status bits */
+void pmc_clear_pmcon_sts(void);
+
 #endif /* _DENVERTON_NS_PM_H_ */

src/soc/intel/denverton_ns/include/soc/pmc.h

@@ -3,9 +3,6 @@
 #ifndef _DENVERTON_NS_PMC_H_
 #define _DENVERTON_NS_PMC_H_
 
-/* PCI Configuration Space (D31:F2): PMC/ACPI */
-#define PCH_PMC_DEV PCI_DEV(0, PMC_DEV, PMC_FUNC)
-
 /* Memory mapped IO registers behind PMC_BASE_ADDRESS */
 #define PMC_ACPI_BASE 0x40 /* IO BAR */
 #define MASK_PMC_ACPI_BASE 0xfffc
@@ -36,14 +33,15 @@
 
 #define PMC_PWRM_BASE   0x48 /* MEM BAR */
 #define   MASK_PMC_PWRM_BASE    0xfffff000 /* 4K alignment */
-#define PMC_GEN_PMCON_A               0xA0
+#define GEN_PMCON_A               0xA0
-#define PMC_GEN_PMCON_B               0xA4
+#define   MS4V                    (1 << 18)
-#define   PMC_GEN_PMCON_B_RTC_PWR_STS   0x04
+#define GEN_PMCON_B               0xA4
-#define   PMC_GEN_PMCON_B_PWR_FLR       0x02
+#define   GEN_PMCON_B_RTC_PWR_STS   0x04
-#define   PMC_GEN_PMCON_B_AFTERG3_EN    0x00
+#define   GEN_PMCON_B_PWR_FLR       0x02
-#define PMC_ETR3                      0xAC
+#define   GEN_PMCON_B_AFTERG3_EN    0x00
-#define   PMC_ETR3_CF9LOCK              BIT31 ///< CF9h Lockdown
+#define ETR3                      0xAC
-#define   PMC_ETR3_CF9GR                BIT20 ///< CF9h Global Reset
+#define   ETR3_CF9LOCK              BIT31 ///< CF9h Lockdown
+#define   ETR3_CF9GR                BIT20 ///< CF9h Global Reset
 
 /* IO Mapped registers behind ACPI_BASE_ADDRESS */
 #define PM1_STS 0x00

src/soc/intel/denverton_ns/pmutil.c

@@ -1,12 +1,16 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#define __SIMPLE_DEVICE__
+
 #include <stdint.h>
 #include <arch/io.h>
 #include <console/console.h>
-
+#include <device/pci.h>
+#include <intelblocks/pmclib.h>
 #include <soc/iomap.h>
-#include <soc/soc_util.h>
+#include <soc/pci_devs.h>
 #include <soc/pm.h>
+#include <soc/soc_util.h>
 
 static void print_num_status_bits(int num_bits, uint32_t status,
 				  const char *const bit_names[])
@@ -231,3 +235,18 @@ static uint32_t print_gpe_sts(uint32_t gpe_sts)
 uint32_t clear_gpe_status(void) { return print_gpe_sts(reset_gpe_status()); }
 
 void clear_pmc_status(void) { /* TODO */ }
+
+void pmc_clear_pmcon_sts(void)
+{
+	uint32_t reg_val;
+	const pci_devfn_t dev = PCH_DEV_PMC;
+
+	reg_val = pci_read_config32(dev, GEN_PMCON_A);
+	/*
+	 * Clear SUS_PWR_FLR, GBL_RST_STS, HOST_RST_STS, PWR_FLR bits
+	 * while retaining MS4V write-1-to-clear bit
+	 */
+	reg_val &= ~(MS4V);
+
+	pci_write_config32(dev, GEN_PMCON_A, reg_val);
+}

src/soc/intel/denverton_ns/romstage.c

@@ -36,7 +36,7 @@ static void display_fsp_smbios_memory_info_hob(void)
 static void early_pmc_init(void)
 {
 	/* PMC (B0:D31:F2). */
-	pci_devfn_t dev = PCH_PMC_DEV;
+	pci_devfn_t dev = PCH_DEV_PMC;
 
 	/* Is PMC present */
 	if (pci_read_config16(dev, 0) == 0xffff) {
@@ -66,16 +66,16 @@ static void early_pmc_init(void)
 	   Status : Plan Fix.
 	*/
 	if (silicon_stepping() == SILICON_REV_DENVERTON_B0) {
-		if (!(pci_read_config32(dev, PMC_GEN_PMCON_B)
+		if (!(pci_read_config32(dev, GEN_PMCON_B)
-					& PMC_GEN_PMCON_B_RTC_PWR_STS)) {
+					& GEN_PMCON_B_RTC_PWR_STS)) {
 			if (read32((void *)(pwrm_base + 0x124))
 				   & ((1 << 11) | (1 << 12))) {
 				/* Performs a global reset */
 				printk(BIOS_DEBUG,
 					"Requesting Global Reset...\n");
-				pci_write_config32(dev, PMC_ETR3,
+				pci_write_config32(dev, ETR3,
-					pci_read_config32(dev, PMC_ETR3)
+					pci_read_config32(dev, ETR3)
-					| PMC_ETR3_CF9GR);
+					| ETR3_CF9GR);
 				full_reset();
 			}
 		}