fsp: Move fsp to fsp1_0

Prepare for FSP 1.1 integration by moving the FSP to a FSP 1.0 specific
directory. See follow-on patches for sharing of common code.

Change-Id: Ic58cb4074c65b91d119909132a012876d7ee7b74
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/9970
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/Kconfig

@@ -335,7 +335,7 @@ source "src/ec/acpi/Kconfig"
 source "src/ec/*/*/Kconfig"
 comment "SoC"
 source "src/soc/*/*/Kconfig"
-source "src/drivers/intel/fsp/Kconfig"
+source "src/drivers/intel/fsp1_0/Kconfig"
 
 endmenu
 

src/cpu/Makefile.inc

@@ -30,7 +30,7 @@ cpu_ucode_cbfs_file = $(obj)/cpu_microcode_blob.bin
 cbfs_include_ucode = y
 endif
 
-ifeq ($(CONFIG_PLATFORM_USES_FSP), y)
+ifeq ($(CONFIG_PLATFORM_USES_FSP1_0), y)
 cpu_ucode_cbfs_offset = "-b $(CONFIG_CPU_MICROCODE_CBFS_LOC)"
 else
 cpu_ucode_cbfs_offset = "-b"

src/cpu/intel/fsp_model_206ax/Kconfig

@@ -28,7 +28,7 @@ if CPU_INTEL_FSP_MODEL_206AX || CPU_INTEL_FSP_MODEL_306AX
 
 config CPU_SPECIFIC_OPTIONS
 	def_bool y
-	select PLATFORM_USES_FSP
+	select PLATFORM_USES_FSP1_0
 	select ARCH_BOOTBLOCK_X86_32
 	select ARCH_VERSTAGE_X86_32
 	select ARCH_ROMSTAGE_X86_32

src/cpu/intel/fsp_model_406dx/Kconfig

@@ -24,7 +24,7 @@ if CPU_INTEL_FSP_MODEL_406DX
 
 config CPU_SPECIFIC_OPTIONS
 	def_bool y
-	select PLATFORM_USES_FSP
+	select PLATFORM_USES_FSP1_0
 	select ARCH_BOOTBLOCK_X86_32
 	select ARCH_VERSTAGE_X86_32
 	select ARCH_ROMSTAGE_X86_32

src/cpu/x86/Kconfig

@@ -105,12 +105,12 @@ config X86_AMD_FIXED_MTRRS
 	  This option informs the MTRR code to use the RdMem and WrMem fields
 	  in the fixed MTRR MSRs.
 
-config PLATFORM_USES_FSP
+config PLATFORM_USES_FSP1_0
 	bool
 	default n
 	help
 	  Selected for Intel processors/platform combinations that use the
-	  Intel Firmware Support Package (FSP) for initialization.
+	  Intel Firmware Support Package (FSP) 1.0 for initialization.
 
 config PARALLEL_MP
 	def_bool n

src/cpu/x86/car.c

@@ -23,8 +23,8 @@
 #include <cbmem.h>
 #include <arch/early_variables.h>
 
-#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP)
-#include <drivers/intel/fsp/fsp_util.h>
+#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_0)
+#include <drivers/intel/fsp1_0/fsp_util.h>
 #endif
 typedef void (* const car_migration_func_t)(void);
 
@@ -67,7 +67,7 @@ void *car_get_var_ptr(void *var)
 		return var;
 	}
 
-#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP)
+#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_0)
 	migrated_base=(char *)find_saved_temp_mem(
 			*(void **)CBMEM_FSP_HOB_PTR);
 #else
@@ -100,7 +100,7 @@ void *car_sync_var_ptr(void *var)
 	if (*mig_var < _car_start || *mig_var > _car_end)
 		return mig_var;
 
-#if !IS_ENABLED(CONFIG_PLATFORM_USES_FSP)
+#if !IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_0)
 	/* Keep console buffer in CAR until cbmemc_reinit() moves it. */
 	if (*mig_var == _car_end)
 		return mig_var;
@@ -149,7 +149,7 @@ static void do_car_migrate_hooks(void)
 
 void car_migrate_variables(void)
 {
-	if (!IS_ENABLED(PLATFORM_USES_FSP))
+	if (!IS_ENABLED(PLATFORM_USES_FSP1_0))
 		do_car_migrate_variables();
 
 	do_car_migrate_hooks();

src/drivers/intel/Makefile.inc

@@ -1,4 +1,4 @@
 subdirs-y += gma
 subdirs-y += wifi
-subdirs-$(CONFIG_PLATFORM_USES_FSP) += fsp
+subdirs-$(CONFIG_PLATFORM_USES_FSP1_0) += fsp1_0
 subdirs-$(CONFIG_DRIVER_INTEL_I210) += i210

src/drivers/intel/fsp1_0/Kconfig

@@ -17,7 +17,7 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
 ##
 
-if PLATFORM_USES_FSP
+if PLATFORM_USES_FSP1_0
 
 comment "Intel FSP"
 
@@ -142,4 +142,4 @@ config FSP_USES_UPD
 	default n
 	help
 	  If this FSP uses UPD/VPD data regions, select this in the chipset Kconfig.
-endif #PLATFORM_USES_FSP
+endif #PLATFORM_USES_FSP1_0

src/drivers/intel/fsp1_0/Makefile.inc

@@ -23,10 +23,10 @@ romstage-y += fsp_util.c hob.c
 ramstage-$(CONFIG_ENABLE_MRC_CACHE) += fastboot_cache.c
 romstage-$(CONFIG_ENABLE_MRC_CACHE) += fastboot_cache.c
 
-CPPFLAGS_common += -Isrc/drivers/intel/fsp
+CPPFLAGS_common += -Isrc/drivers/intel/fsp1_0
 
 ifeq ($(CONFIG_USE_GENERIC_FSP_CAR_INC),y)
-cpu_incs += $(src)/drivers/intel/fsp/cache_as_ram.inc
+cpu_incs += $(src)/drivers/intel/fsp1_0/cache_as_ram.inc
 endif
 
 ifeq ($(CONFIG_HAVE_FSP_BIN),y)

src/mainboard/intel/bayleybay_fsp/romstage.c

@@ -36,7 +36,7 @@
 #include <baytrail/romstage.h>
 #include <baytrail/acpi.h>
 #include <baytrail/baytrail.h>
-#include <drivers/intel/fsp/fsp_util.h>
+#include <drivers/intel/fsp1_0/fsp_util.h>
 
 /**
  * /brief mainboard call for setup that needs to be done before fsp init

src/mainboard/intel/minnowmax/romstage.c

@@ -20,7 +20,7 @@
  */
 
 #include <baytrail/romstage.h>
-#include <drivers/intel/fsp/fsp_util.h>
+#include <drivers/intel/fsp1_0/fsp_util.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
 #include <baytrail/gpio.h>

src/mainboard/intel/mohonpeak/romstage.c

@@ -23,7 +23,7 @@
 #include <device/pci_def.h>
 #include <device/pnp_def.h>
 #include <cpu/x86/lapic.h>
-#include <drivers/intel/fsp/fsp_util.h>
+#include <drivers/intel/fsp1_0/fsp_util.h>
 #include <southbridge/intel/fsp_rangeley/soc.h>
 #include <southbridge/intel/fsp_rangeley/gpio.h>
 #include <southbridge/intel/fsp_rangeley/romstage.h>

src/mainboard/siemens/mc_tcu3/romstage.c

@@ -36,7 +36,7 @@
 #include <baytrail/romstage.h>
 #include <baytrail/acpi.h>
 #include <baytrail/baytrail.h>
-#include <drivers/intel/fsp/fsp_util.h>
+#include <drivers/intel/fsp1_0/fsp_util.h>
 #include "modhwinfo.h"
 
 /**

src/northbridge/intel/fsp_rangeley/chip.h

@@ -22,7 +22,7 @@
 #define _FSP_RANGELEY_CHIP_H_
 
 #include <arch/acpi.h>
-#include <drivers/intel/fsp/fsp_values.h>
+#include <drivers/intel/fsp1_0/fsp_values.h>
 
 struct northbridge_intel_fsp_rangeley_config {
 

src/northbridge/intel/fsp_rangeley/fsp/Kconfig

@@ -19,7 +19,7 @@
 
 config RANGELEY_FSP_SPECIFIC_OPTIONS
 	def_bool y
-	select PLATFORM_USES_FSP
+	select PLATFORM_USES_FSP1_0
 	select USE_GENERIC_FSP_CAR_INC
 	select FSP_USES_UPD
 	select ENABLE_MRC_CACHE #rangeley FSP always needs MRC data

src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c

@@ -25,7 +25,7 @@
 #include <cbmem.h>
 #include <device/device.h>
 #include <southbridge/intel/fsp_rangeley/pci_devs.h>
-#include <drivers/intel/fsp/fsp_util.h>
+#include <drivers/intel/fsp1_0/fsp_util.h>
 #include <fspvpd.h>
 #include <fspbootmode.h>
 #include <reset.h>

src/northbridge/intel/fsp_rangeley/northbridge.c

@@ -35,7 +35,7 @@
 #include <cbmem.h>
 #include "chip.h"
 #include "northbridge.h"
-#include <drivers/intel/fsp/fsp_util.h>
+#include <drivers/intel/fsp1_0/fsp_util.h>
 #include <cpu/x86/lapic.h>
 
 static int bridge_revision_id = -1;

src/northbridge/intel/fsp_rangeley/raminit.c

@@ -24,7 +24,7 @@
 #include <cbmem.h>
 #include <device/pci_def.h>
 #include "northbridge.h"
-#include <drivers/intel/fsp/fsp_util.h>
+#include <drivers/intel/fsp1_0/fsp_util.h>
 
 static uintptr_t smm_region_start(void)
 {

src/northbridge/intel/fsp_sandybridge/fsp/Kconfig

@@ -19,7 +19,7 @@
 
 config SANDYBRIDGE_FSP_SPECIFIC_OPTIONS
 	def_bool y
-	select PLATFORM_USES_FSP
+	select PLATFORM_USES_FSP1_0
 	select USE_GENERIC_FSP_CAR_INC
 	select FSP_USES_UPD if SOUTHBRIDGE_INTEL_FSP_I89XX
 

src/soc/intel/fsp_baytrail/baytrail/romstage.h

@@ -29,7 +29,7 @@ void report_platform_info(void);
 
 #include <stdint.h>
 #include <arch/cpu.h>
-#include <drivers/intel/fsp/fsp_util.h>
+#include <drivers/intel/fsp1_0/fsp_util.h>
 
 void main(FSP_INFO_HEADER *fsp_info_header);
 void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr);

src/soc/intel/fsp_baytrail/chip.c

@@ -22,7 +22,7 @@
 #include <device/pci.h>
 #include <baytrail/pci_devs.h>
 #include <baytrail/ramstage.h>
-#include <drivers/intel/fsp/fsp_util.h>
+#include <drivers/intel/fsp1_0/fsp_util.h>
 #include "chip.h"
 
 static void pci_domain_set_resources(device_t dev)

src/soc/intel/fsp_baytrail/chip.h

@@ -23,7 +23,7 @@
 #define _FSP_BAYTRAIL_CHIP_H_
 
 #include <arch/acpi.h>
-#include <drivers/intel/fsp/fsp_values.h>
+#include <drivers/intel/fsp1_0/fsp_values.h>
 
 /* The devicetree parser expects chip.h to reside directly in the path
  * specified by the devicetree. */

src/soc/intel/fsp_baytrail/fsp/Kconfig

@@ -19,7 +19,7 @@
 
 config BAYTRAIL_FSP_SPECIFIC_OPTIONS
 	def_bool y
-	select PLATFORM_USES_FSP
+	select PLATFORM_USES_FSP1_0
 	select USE_GENERIC_FSP_CAR_INC
 	select FSP_USES_UPD
 

src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c

@@ -26,7 +26,7 @@
 #include <device/device.h>
 #include <device/pci_def.h>
 #include <baytrail/pci_devs.h>
-#include <drivers/intel/fsp/fsp_util.h>
+#include <drivers/intel/fsp1_0/fsp_util.h>
 #include "../chip.h"
 #include <arch/io.h>
 #include <baytrail/reset.h>

src/soc/intel/fsp_baytrail/memmap.c

@@ -22,7 +22,7 @@
 #include <cbmem.h>
 #include <baytrail/iosf.h>
 #include <baytrail/smm.h>
-#include <drivers/intel/fsp/fsp_util.h>
+#include <drivers/intel/fsp1_0/fsp_util.h>
 
 uintptr_t smm_region_start(void)
 {

src/soc/intel/fsp_baytrail/northcluster.c

@@ -31,7 +31,7 @@
 #include <device/pci.h>
 #include <cbmem.h>
 #include <baytrail/baytrail.h>
-#include <drivers/intel/fsp/fsp_util.h>
+#include <drivers/intel/fsp1_0/fsp_util.h>
 
 
 static const int legacy_hole_base_k = 0xa0000 / 1024;

src/soc/intel/fsp_baytrail/romstage/romstage.c

@@ -37,7 +37,7 @@
 #include <baytrail/romstage.h>
 #include <baytrail/acpi.h>
 #include <baytrail/baytrail.h>
-#include <drivers/intel/fsp/fsp_util.h>
+#include <drivers/intel/fsp1_0/fsp_util.h>
 #include <baytrail/pmc.h>
 #include <baytrail/spi.h>
 #include <version.h>

src/southbridge/intel/fsp_rangeley/romstage.c

@@ -29,7 +29,7 @@
 #include <pc80/mc146818rtc.h>
 #include <cbmem.h>
 #include <console/console.h>
-#include <drivers/intel/fsp/fsp_util.h>
+#include <drivers/intel/fsp1_0/fsp_util.h>
 #include "northbridge/intel/fsp_rangeley/northbridge.h"
 #include "southbridge/intel/fsp_rangeley/soc.h"
 #include "southbridge/intel/fsp_rangeley/gpio.h"

src/southbridge/intel/fsp_rangeley/romstage.h

@@ -27,7 +27,7 @@
 
 #include <stdint.h>
 #include <arch/cpu.h>
-#include <drivers/intel/fsp/fsp_util.h>
+#include <drivers/intel/fsp1_0/fsp_util.h>
 
 void main(FSP_INFO_HEADER *fsp_info_header);
 void early_mainboard_romstage_entry(void);

src/vendorcode/intel/Kconfig

@@ -19,7 +19,7 @@
 
 config FSP_VENDORCODE_HEADER_PATH
 	string
-	default "fsp/ivybridge_bd82x6x" if CPU_INTEL_FSP_MODEL_306AX && SOUTHBRIDGE_INTEL_FSP_BD82X6X
-	default "fsp/ivybridge_i89xx" if CPU_INTEL_FSP_MODEL_306AX && SOUTHBRIDGE_INTEL_FSP_I89XX
-	default "fsp/baytrail" if SOC_INTEL_FSP_BAYTRAIL
-	default "fsp/rangeley" if CPU_INTEL_FSP_MODEL_406DX
+	default "fsp1_0/ivybridge_bd82x6x" if CPU_INTEL_FSP_MODEL_306AX && SOUTHBRIDGE_INTEL_FSP_BD82X6X
+	default "fsp1_0/ivybridge_i89xx" if CPU_INTEL_FSP_MODEL_306AX && SOUTHBRIDGE_INTEL_FSP_I89XX
+	default "fsp1_0/baytrail" if SOC_INTEL_FSP_BAYTRAIL
+	default "fsp1_0/rangeley" if CPU_INTEL_FSP_MODEL_406DX