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nehalem: Fix SMRAM register address 

Change-Id: If6646853039d15d6ba0fcf2b9b9b0658004be6e6
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4787
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
This commit is contained in:
Vladimir Serbinenko 2014-01-02 10:16:46 +01:00
parent 969f8617e9
commit 786c0f5fca
2 changed files with 5 additions and 6 deletions
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4
src/northbridge/intel/nehalem/nehalem.h
View File

@ -219,8 +219,6 @@ enum {
#define QPD0F1_PAM(x) (0x40+(x)) /* 0-6*/
#define D0F0_REMAPBASE 0x98
#define D0F0_REMAPLIMIT 0x9a
#define D0F0_SMRAM 0x9d
#define D0F0_ESMRAMC 0x9e
#define D0F0_TOM 0xa0
#define D0F0_TOUUD 0xa2
#define D0F0_IGD_BASE 0xa4
@ -477,7 +475,7 @@ void init_iommu(void);
#define X60BAR 0x60
#define LAC 0x87 /* Legacy Access Control */
#define SMRAM 0x88 /* System Management RAM Control */
#define QPD0F1_SMRAM 0x4d /* System Management RAM Control */
#define D_OPEN (1 << 6)
#define D_CLS (1 << 5)
#define D_LCK (1 << 4)

7
src/southbridge/intel/ibexpeak/smi.c
View File

@ -334,6 +334,7 @@ static int smm_handler_copied = 0;
static void smm_install(void)
{
device_t dev = PCI_DEV(0, 0, 0);
device_t qpdev = PCI_DEV(QUICKPATH_BUS, 0, 1);
u32 smm_base = 0xa0000;
struct ied_header ied = {
.signature = "INTEL RSVD",
@ -349,7 +350,7 @@ static void smm_install(void)
smm_handler_copied = 1;
/* enable the SMM memory window */
pci_write_config8(dev, SMRAM, D_OPEN | G_SMRAME | C_BASE_SEG);
pci_write_config8(qpdev, QPD0F1_SMRAM, D_OPEN | G_SMRAME | C_BASE_SEG);
#if CONFIG_SMM_TSEG
smm_base = pci_read_config32(dev, TSEG) & ~1;
@ -371,7 +372,7 @@ static void smm_install(void)
wbinvd();
/* close the SMM memory window and enable normal SMM */
pci_write_config8(dev, SMRAM, G_SMRAME | C_BASE_SEG);
pci_write_config8(qpdev, QPD0F1_SMRAM, G_SMRAME | C_BASE_SEG);
}
void smm_init(void)
@ -398,7 +399,7 @@ void smm_lock(void)
* make the SMM registers writable again.
*/
printk(BIOS_DEBUG, "Locking SMM.\n");
pci_write_config8(PCI_DEV(0, 0, 0), SMRAM,
pci_write_config8(PCI_DEV(QUICKPATH_BUS, 0, 1), QPD0F1_SMRAM,
D_LCK | G_SMRAME | C_BASE_SEG);
}