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mb/intel/adlrvp: Set power limits dynamically for ADL-N SKUs 

This patch adds support for the ADL-N SKUs based on the PCH ID.
Document reference: 645548 (ADL-N EDS Volume 1).

BUG=None
BRANCH=None
TEST=Build FW and test on adln_rvp board

Signed-off-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com>
Change-Id: Ie49398b8a7de8d8cff3536eae6a5e893980f9c26
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64569
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
This commit is contained in:
Vidya Gopalakrishnan 2022-05-22 10:42:39 +05:30 committed by Paul Fagerburg
parent 37a55d16fc
commit 7870a353df
1 changed files with 4 additions and 0 deletions
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4
src/mainboard/intel/adlrvp/ramstage.c
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@ -21,6 +21,10 @@ const struct cpu_power_limits limits[] = {
{ PCI_DID_INTEL_ADL_P_ID_5, 28, 4000, 28000, 64000, 64000, 140000 }, { PCI_DID_INTEL_ADL_P_ID_5, 28, 4000, 28000, 64000, 64000, 140000 },
{ PCI_DID_INTEL_ADL_P_ID_3, 28, 4000, 28000, 64000, 64000, 140000 }, { PCI_DID_INTEL_ADL_P_ID_3, 28, 4000, 28000, 64000, 64000, 140000 },
{ PCI_DID_INTEL_ADL_P_ID_3, 45, 5000, 45000, 115000, 115000, 215000 }, { PCI_DID_INTEL_ADL_P_ID_3, 45, 5000, 45000, 115000, 115000, 215000 },
{ PCI_DID_INTEL_ADL_N_ID_1, 15, 3000, 15000, 35000, 35000, 83000 },
{ PCI_DID_INTEL_ADL_N_ID_2, 6, 3000, 6000, 25000, 25000, 78000 },
{ PCI_DID_INTEL_ADL_N_ID_3, 6, 3000, 6000, 25000, 25000, 78000 },
{ PCI_DID_INTEL_ADL_N_ID_4, 6, 3000, 6000, 25000, 25000, 78000 },
}; };
WEAK_DEV_PTR(dptf_policy); WEAK_DEV_PTR(dptf_policy);