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vc/amd/fsp/mendocino/FspmUpd: Add UPD to set eDP panel T9 vaule 

Add UPD edp_panel_t9_ms for eDP panel sequence adjustment.

BUG=b:271704149
BRANCH=Skyrim
Test=Build/Boot to ChromeOS

Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: Idc1a212e9c203584a6497fd6cbd3f995eeb030f2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74788
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Chris Wang 2023-04-26 19:42:50 +08:00 committed by Martin L Roth
parent c2059fa72a
commit 78790c872c
1 changed files with 2 additions and 1 deletions
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3
src/vendorcode/amd/fsp/mendocino/FspmUpd.h
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@ -102,7 +102,8 @@ typedef struct __packed {
/** Offset 0x04E5**/ uint32_t vrm_soc_current_limit_mA; /** Offset 0x04E5**/ uint32_t vrm_soc_current_limit_mA;
/** Offset 0x04E9**/ uint8_t fch_usb_3_port_force_gen1; /** Offset 0x04E9**/ uint8_t fch_usb_3_port_force_gen1;
/** Offset 0x04EA**/ uint8_t edp_panel_t8_ms; /** Offset 0x04EA**/ uint8_t edp_panel_t8_ms;
/** Offset 0x04EB**/ uint8_t UnusedUpdSpace2[277]; /** Offset 0x04EB**/ uint8_t edp_panel_t9_ms;
/** Offset 0x04EC**/ uint8_t UnusedUpdSpace2[276];
/** Offset 0x0600**/ uint16_t UpdTerminator; /** Offset 0x0600**/ uint16_t UpdTerminator;
} FSP_M_CONFIG; } FSP_M_CONFIG;