From 7896b8ce59f88d7cd65bf7c9dfc3f9b1f9f2c640 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Fri, 19 Jun 2020 17:15:51 +0200 Subject: [PATCH] mb/protectli/vault_kbl: Enable Intel PTT MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit TEST=tweak PCR banks in SeaBIOS TPM menu, run tpm2_pcrlist in Linux Signed-off-by: Michał Żygowski Change-Id: I7c443a25ca7259df9c0a07615d0502f47d25792e Reviewed-on: https://review.coreboot.org/c/coreboot/+/42565 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/mainboard/protectli/vault_kbl/Kconfig | 3 +++ src/mainboard/protectli/vault_kbl/devicetree.cb | 3 +++ 2 files changed, 6 insertions(+) diff --git a/src/mainboard/protectli/vault_kbl/Kconfig b/src/mainboard/protectli/vault_kbl/Kconfig index 8c09a60b6e..518bb6dca5 100644 --- a/src/mainboard/protectli/vault_kbl/Kconfig +++ b/src/mainboard/protectli/vault_kbl/Kconfig @@ -11,6 +11,9 @@ config BOARD_SPECIFIC_OPTIONS select SOC_INTEL_KABYLAKE select SPI_FLASH_MACRONIX select SUPERIO_ITE_IT8772F + select MAINBOARD_HAS_CRB_TPM + select HAVE_INTEL_PTT + select TPM2 config IRQ_SLOT_COUNT int diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb index d3e8b2305c..bb408a4351 100644 --- a/src/mainboard/protectli/vault_kbl/devicetree.cb +++ b/src/mainboard/protectli/vault_kbl/devicetree.cb @@ -305,4 +305,7 @@ chip soc/intel/skylake device pci 1f.5 off end # PCH SPI device pci 1f.6 off end # GbE end + chip drivers/crb + device mmio 0xfed40000 on end + end end