soc/amd/picasso: Mark FCH MMIO addresses as non-posted

Immediately following FSP-S, update the data fabric routing
registers to make the region between HPET and LAPIC as non-posted.

If AGESA is modified to do this, we can delete data_fabric_util.c. If
AGESA is modified to not program the registers, then we can simplify
data_fabric_set_mmio_np().

BUG=b:147042464, b:156296146
TEST=boot trembyle

Change-Id: Idbafaac158f5a4c533d2d88db79bb4d6244e5355
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41268
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/amd/picasso/Makefile.inc

@@ -44,6 +44,7 @@ verstage-y += tsc_freq.c
 ramstage-y += i2c.c
 ramstage-y += chip.c
 ramstage-y += cpu.c
+ramstage-y += data_fabric_util.c
 ramstage-y += mca.c
 ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
 ramstage-y += gpio.c

src/soc/amd/picasso/chip.c

@@ -8,6 +8,7 @@
 #include <romstage_handoff.h>
 #include <soc/acpi.h>
 #include <soc/cpu.h>
+#include <soc/data_fabric.h>
 #include <soc/pci_devs.h>
 #include <soc/southbridge.h>
 #include "chip.h"
@@ -100,6 +101,7 @@ static void soc_init(void *chip_info)
 {
 	fsp_silicon_init(acpi_is_wakeup_s3());
 
+	data_fabric_set_mmio_np();
 	southbridge_init(chip_info);
 	setup_bsp_ramtop();
 }

src/soc/amd/picasso/data_fabric_util.c

@@ -0,0 +1,117 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include <cpu/x86/lapic_def.h>
+#include <device/pci_ops.h>
+#include <soc/data_fabric.h>
+#include <soc/iomap.h>
+#include <soc/pci_devs.h>
+#include <stdbool.h>
+
+static void disable_mmio_reg(int reg)
+{
+	pci_write_config32(SOC_DF_F0_DEV, NB_MMIO_CONTROL(reg),
+			   IOMS0_FABRIC_ID << MMIO_DST_FABRIC_ID_SHIFT);
+	pci_write_config32(SOC_DF_F0_DEV, NB_MMIO_BASE(reg), 0);
+	pci_write_config32(SOC_DF_F0_DEV, NB_MMIO_LIMIT(reg), 0);
+}
+
+static bool is_mmio_reg_disabled(int reg)
+{
+	uint32_t val = pci_read_config32(SOC_DF_F0_DEV, NB_MMIO_CONTROL(reg));
+	return !(val & ((MMIO_WE | MMIO_RE)));
+}
+
+static int find_unused_mmio_reg(void)
+{
+	unsigned int i;
+
+	for (i = 0; i < NUM_NB_MMIO_REGS; i++) {
+		if (is_mmio_reg_disabled(i))
+			return i;
+	}
+	return -1;
+}
+
+void data_fabric_set_mmio_np(void)
+{
+	/*
+	 * Mark region from HPET-LAPIC or 0xfed00000-0xfee00000-1 as NP.
+	 *
+	 * AGESA has already programmed the NB MMIO routing, however nothing
+	 * is yet marked as non-posted.
+	 *
+	 * If there exists an overlapping routing base/limit pair, trim its
+	 * base or limit to avoid the new NP region.  If any pair exists
+	 * completely within HPET-LAPIC range, remove it.  If any pair surrounds
+	 * HPET-LAPIC, it must be split into two regions.
+	 *
+	 * TODO(b/156296146): Remove the settings from AGESA and allow coreboot
+	 * to own everything.  If not practical, consider erasing all settings
+	 * and have coreboot reprogram them.  At that time, make the source
+	 * below more flexible.
+	 *   * Note that the code relies on the granularity of the HPET and
+	 *     LAPIC addresses being sufficiently large that the shifted limits
+	 *     +/-1 are always equivalent to the non-shifted values +/-1.
+	 */
+
+	unsigned int i;
+	int reg;
+	uint32_t base, limit, ctrl;
+	const uint32_t np_bot = HPET_BASE_ADDRESS >> D18F0_MMIO_SHIFT;
+	const uint32_t np_top = (LOCAL_APIC_ADDR - 1) >> D18F0_MMIO_SHIFT;
+
+	for (i = 0; i < NUM_NB_MMIO_REGS; i++) {
+		/* Adjust all registers that overlap */
+		ctrl = pci_read_config32(SOC_DF_F0_DEV, NB_MMIO_CONTROL(i));
+		if (!(ctrl & (MMIO_WE | MMIO_RE)))
+			continue; /* not enabled */
+
+		base = pci_read_config32(SOC_DF_F0_DEV, NB_MMIO_BASE(i));
+		limit = pci_read_config32(SOC_DF_F0_DEV, NB_MMIO_LIMIT(i));
+
+		if (base > np_top || limit < np_bot)
+			continue; /* no overlap at all */
+
+		if (base >= np_bot && limit <= np_top) {
+			disable_mmio_reg(i); /* 100% within, so remove */
+			continue;
+		}
+
+		if (base < np_bot && limit > np_top) {
+			/* Split the configured region */
+			pci_write_config32(SOC_DF_F0_DEV, NB_MMIO_LIMIT(i), np_bot - 1);
+			reg = find_unused_mmio_reg();
+			if (reg < 0) {
+				/* Although a pair could be freed later, this condition is
+				 * very unusual and deserves analysis.  Flag an error and
+				 * leave the topmost part unconfigured. */
+				printk(BIOS_ERR,
+				       "Error: Not enough NB MMIO routing registers\n");
+				continue;
+			}
+			pci_write_config32(SOC_DF_F0_DEV, NB_MMIO_BASE(reg), np_top + 1);
+			pci_write_config32(SOC_DF_F0_DEV, NB_MMIO_LIMIT(reg), limit);
+			pci_write_config32(SOC_DF_F0_DEV, NB_MMIO_CONTROL(reg), ctrl);
+			continue;
+		}
+
+		/* If still here, adjust only the base or limit */
+		if (base <= np_bot)
+			pci_write_config32(SOC_DF_F0_DEV, NB_MMIO_LIMIT(i), np_bot - 1);
+		else
+			pci_write_config32(SOC_DF_F0_DEV, NB_MMIO_BASE(i), np_top + 1);
+	}
+
+	reg = find_unused_mmio_reg();
+	if (reg < 0) {
+		printk(BIOS_ERR, "Error: cannot configure region as NP\n");
+		return;
+	}
+
+	pci_write_config32(SOC_DF_F0_DEV, NB_MMIO_BASE(reg), np_bot);
+	pci_write_config32(SOC_DF_F0_DEV, NB_MMIO_LIMIT(reg), np_top);
+	pci_write_config32(SOC_DF_F0_DEV, NB_MMIO_CONTROL(reg),
+			   (IOMS0_FABRIC_ID << MMIO_DST_FABRIC_ID_SHIFT) | MMIO_NP | MMIO_WE
+				   | MMIO_RE);
+}

src/soc/amd/picasso/include/soc/data_fabric.h

@@ -24,4 +24,6 @@
 #define NB_MMIO_LIMIT(reg)		((reg) * 4 * sizeof(uint32_t) + D18F0_MMIO_LIMIT0)
 #define NB_MMIO_CONTROL(reg)		((reg) * 4 * sizeof(uint32_t) + D18F0_MMIO_CTRL0)
 
+void data_fabric_set_mmio_np(void);
+
 #endif /* __SOC_PICASSO_DATAFABRIC_H__ */