diff --git a/src/drivers/amd/agesa/eventlog.c b/src/drivers/amd/agesa/eventlog.c index 49ab4ce1c8..126a2ee1e1 100644 --- a/src/drivers/amd/agesa/eventlog.c +++ b/src/drivers/amd/agesa/eventlog.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include @@ -97,7 +98,7 @@ void agesa_state_on_entry(struct agesa_state *task, AGESA_STRUCT_NAME func) { int i; - task->apic_id = (u8) (cpuid_ebx(1) >> 24); + task->apic_id = (u8)initial_lapicid(); task->func = func; task->function_name = undefined; diff --git a/src/drivers/amd/agesa/romstage.c b/src/drivers/amd/agesa/romstage.c index 29423ef1ba..b8f38ce4ee 100644 --- a/src/drivers/amd/agesa/romstage.c +++ b/src/drivers/amd/agesa/romstage.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -35,7 +36,7 @@ static void romstage_main(void) struct postcar_frame pcf; struct sysinfo romstage_state; struct sysinfo *cb = &romstage_state; - u8 initial_apic_id = (u8) (cpuid_ebx(1) >> 24); + unsigned int initial_apic_id = initial_lapicid(); int cbmem_initted = 0; fill_sysinfo(cb); @@ -49,7 +50,7 @@ static void romstage_main(void) console_init(); } - printk(BIOS_DEBUG, "APIC %02d: CPU Family_Model = %08x\n", + printk(BIOS_DEBUG, "APIC %02u: CPU Family_Model = %08x\n", initial_apic_id, cpuid_eax(1)); set_ap_entry_ptr(ap_romstage_main); diff --git a/src/soc/amd/picasso/mca.c b/src/soc/amd/picasso/mca.c index acb248d2f4..65b1916112 100644 --- a/src/soc/amd/picasso/mca.c +++ b/src/soc/amd/picasso/mca.c @@ -2,6 +2,7 @@ #include #include +#include #include #include #include @@ -160,10 +161,8 @@ void check_mca(void) for (i = 0 ; i < num_banks ; i++) { mci.sts = rdmsr(MCAX_STATUS_MSR(i)); if (mci.sts.hi || mci.sts.lo) { - int core = cpuid_ebx(1) >> 24; - - printk(BIOS_WARNING, "#MC Error: core %d, bank %d %s\n", - core, i, + printk(BIOS_WARNING, "#MC Error: core %u, bank %d %s\n", + initial_lapicid(), i, i < ARRAY_SIZE(mca_bank_name) ? mca_bank_name[i] : ""); printk(BIOS_WARNING, " MC%d_STATUS = %08x_%08x\n", diff --git a/src/soc/amd/stoneyridge/mca.c b/src/soc/amd/stoneyridge/mca.c index db5fabc389..1523563d0c 100644 --- a/src/soc/amd/stoneyridge/mca.c +++ b/src/soc/amd/stoneyridge/mca.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include #include #include #include @@ -163,10 +164,8 @@ void check_mca(void) mci.sts = rdmsr(IA32_MC0_STATUS + (i * 4)); if (mci.sts.hi || mci.sts.lo) { - int core = cpuid_ebx(1) >> 24; - - printk(BIOS_WARNING, "#MC Error: core %d, bank %d %s\n", - core, i, mca_bank_name[i]); + printk(BIOS_WARNING, "#MC Error: core %u, bank %d %s\n", + initial_lapicid(), i, mca_bank_name[i]); printk(BIOS_WARNING, " MC%d_STATUS = %08x_%08x\n", i, mci.sts.hi, mci.sts.lo); diff --git a/src/soc/intel/xeon_sp/smmrelocate.c b/src/soc/intel/xeon_sp/smmrelocate.c index dc4b511ad2..f44fc62d3e 100644 --- a/src/soc/intel/xeon_sp/smmrelocate.c +++ b/src/soc/intel/xeon_sp/smmrelocate.c @@ -2,6 +2,7 @@ #include #include +#include #include #include #include @@ -86,7 +87,6 @@ static void update_save_state(int cpu, uintptr_t curr_smbase, { u32 smbase; u32 iedbase; - int apic_id; em64t101_smm_state_save_area_t *save_state; /* * The relocated handler runs with all CPUs concurrently. Therefore @@ -96,9 +96,8 @@ static void update_save_state(int cpu, uintptr_t curr_smbase, smbase = staggered_smbase; iedbase = relo_params->ied_base; - apic_id = cpuid_ebx(1) >> 24; printk(BIOS_DEBUG, "New SMBASE=0x%08x IEDBASE=0x%08x\n apic_id=0x%x\n", - smbase, iedbase, apic_id); + smbase, iedbase, initial_lapicid()); save_state = (void *)(curr_smbase + SMM_DEFAULT_SIZE - sizeof(*save_state));