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Remove remaining uses of 

HAVE_FAILOVER_BOOT
HAVE_FALLBACK_BOOT
USE_FAILOVER_IMAGE
USE_FALLBACK_IMAGE

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5259 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Patrick Georgi 2010-03-18 20:58:41 +00:00
parent 2bd9100341
commit 78acf93291
42 changed files with 0 additions and 385 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
src/Kconfig
View File

@ -272,22 +272,6 @@ config ACPI_SSDTX_NUM
int
default 0
config HAVE_FALLBACK_BOOT
bool
default y
config USE_FALLBACK_IMAGE
bool
default y
config HAVE_FAILOVER_BOOT
bool
default n
config USE_FAILOVER_IMAGE
bool
default n
config HAVE_HARD_RESET
bool
default y if BOARD_HAS_HARD_RESET

17
src/cpu/amd/car/cache_as_ram.inc
View File

@ -71,9 +71,6 @@ cache_as_ram_setup:
cvtsi2sd %eax, %xmm2
cvtsd2si %xmm3, %ebx
/* hope we can skip the double set for normal part */
#if ((CONFIG_HAVE_FAILOVER_BOOT == 1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT == 0) && (CONFIG_USE_FALLBACK_IMAGE == 1))
/* check if cpu_init_detected */
movl $MTRRdefType_MSR, %ecx
rdmsr
@ -248,15 +245,6 @@ clear_fixed_var_mtrr_out:
xorl %edx, %edx
movl $(((CONFIG_RAMTOP) + TOP_MEM_MASK) & ~TOP_MEM_MASK) , %eax
wrmsr
#endif /* CONFIG_USE_FAILOVER_IMAGE == 1*/
#if ((CONFIG_HAVE_FAILOVER_BOOT == 1) && (CONFIG_USE_FAILOVER_IMAGE == 0)) || ((CONFIG_HAVE_FAILOVER_BOOT == 0) && (CONFIG_USE_FALLBACK_IMAGE == 0))
/* disable cache */
movl %cr0, %eax
orl $(0x1 << 30), %eax
movl %eax, %cr0
#endif
#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
/* enable write base caching so we can do execute in place
@ -283,7 +271,6 @@ wbcache_post_fam10_setup:
wrmsr
#endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
#if ((CONFIG_HAVE_FAILOVER_BOOT == 1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT == 0) && (CONFIG_USE_FALLBACK_IMAGE == 1))
/* Set the default memory type and enable fixed and variable MTRRs */
movl $MTRRdefType_MSR, %ecx
xorl %edx, %edx
@ -296,7 +283,6 @@ wbcache_post_fam10_setup:
rdmsr
orl $(SYSCFG_MSR_MtrrVarDramEn | SYSCFG_MSR_MtrrFixDramEn), %eax
wrmsr
#endif
movb $0xA1, %al
outb %al, $0x80
@ -318,7 +304,6 @@ fam10_end_part1:
movb $0xA2, %al
outb %al, $0x80
#if ((CONFIG_HAVE_FAILOVER_BOOT == 1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT == 0) && (CONFIG_USE_FALLBACK_IMAGE == 1))
/* Read the range with lodsl*/
cld
movl $CacheBase, %esi
@ -331,8 +316,6 @@ fam10_end_part1:
xorl %eax, %eax
rep stosl
#endif /*CONFIG_USE_FAILOVER_IMAGE == 1*/
/* set up the stack pointer */
movl $(CacheBase + CacheSize - GlobalVarSize), %eax
movl %eax, %esp

3
src/cpu/intel/model_106cx/cache_as_ram.inc
View File

@ -29,8 +29,6 @@
movl %eax, %ebp
cache_as_ram:
#if CONFIG_USE_FALLBACK_IMAGE == 1
post_code(0x20)
/* Send INIT IPI to all excluding ourself */
@ -134,7 +132,6 @@ clear_mtrrs:
movl %cr0, %eax
andl $( ~( (1 << 30) | (1 << 29) ) ), %eax
movl %eax, %cr0
#endif
/* Set up stack pointer */
#if defined(CONFIG_USBDEBUG_DIRECT) && (CONFIG_USBDEBUG_DIRECT == 1)

3
src/cpu/intel/model_6ex/cache_as_ram.inc
View File

@ -29,8 +29,6 @@
movl %eax, %ebp
cache_as_ram:
#if CONFIG_USE_FALLBACK_IMAGE == 1
post_code(0x20)
/* Send INIT IPI to all excluding ourself */
@ -123,7 +121,6 @@ clear_mtrrs:
movl %cr0, %eax
andl $( ~( (1 << 30) | (1 << 29) ) ), %eax
movl %eax, %cr0
#endif
/* Set up stack pointer */
#if defined(CONFIG_USBDEBUG_DIRECT) && (CONFIG_USBDEBUG_DIRECT == 1)

3
src/cpu/intel/model_6fx/cache_as_ram.inc
View File

@ -29,8 +29,6 @@
movl %eax, %ebp
cache_as_ram:
#if CONFIG_USE_FALLBACK_IMAGE == 1
post_code(0x20)
/* Send INIT IPI to all excluding ourself */
@ -130,7 +128,6 @@ clear_mtrrs:
movl %cr0, %eax
andl $( ~( (1 << 30) | (1 << 29) ) ), %eax
movl %eax, %cr0
#endif
/* Set up stack pointer */
#if defined(CONFIG_USBDEBUG_DIRECT) && (CONFIG_USBDEBUG_DIRECT == 1)

17
src/cpu/x86/car/cache_as_ram.inc
View File

@ -36,9 +36,6 @@
movl %eax, %ebp
CacheAsRam:
/* hope we can skip the double set for normal part */
#if CONFIG_USE_FALLBACK_IMAGE == 1
// Check whether the processor has HT capability
movl $01, %eax
cpuid
@ -191,14 +188,6 @@ clear_fixed_var_mtrr_out:
simplemask CacheSize, 0
wrmsr
#else
/* disable cache */
movl %cr0, %eax
orl $(0x1 << 30), %eax
movl %eax, %cr0
#endif /* CONFIG_USE_FALLBACK_IMAGE == 1*/
#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
#if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK
#define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
@ -225,8 +214,6 @@ clear_fixed_var_mtrr_out:
andl $0x9fffffff, %eax
movl %eax, %cr0
#if CONFIG_USE_FALLBACK_IMAGE == 1
/* Read the range with lodsl*/
movl $CacheBase, %esi
cld
@ -283,8 +270,6 @@ clear_fixed_var_mtrr_out:
.xout1x:
#endif
#endif /*CONFIG_USE_FALLBACK_IMAGE == 1*/
movl $(CacheBase + CacheSize - 4), %eax
movl %eax, %esp
@ -319,7 +304,6 @@ var_mtrr_msr:
.long 0x20C, 0x20D, 0x20E, 0x20F
.long 0x000 /* NULL, end of table */
#if CONFIG_USE_FALLBACK_IMAGE == 1
.align 0x1000
.code16
.global LogicalAP_SIPI
@ -349,5 +333,4 @@ Halt_LogicalAP:
hlt
jmp Halt_LogicalAP
.code32
#endif /*CONFIG_USE_FALLBACK_IMAGE == 1*/
.CacheAsRam_out:

5
src/include/fallback.h
View File

@ -3,12 +3,7 @@
#ifndef ASSEMBLY
#if CONFIG_HAVE_FALLBACK_BOOT == 1
void set_boot_successful(void);
#else
#define set_boot_successful()
#endif
void boot_successful(void);
#endif /* ASSEMBLY */

2
src/lib/fallback_boot.c
View File

@ -5,7 +5,6 @@
#include <arch/io.h>
#if CONFIG_HAVE_FALLBACK_BOOT == 1
void set_boot_successful(void)
{
/* Remember I succesfully booted by setting
@ -26,7 +25,6 @@ void set_boot_successful(void)
byte &= 0x0f;
outb(byte, RTC_PORT(1));
}
#endif
void boot_successful(void)
{

9
src/mainboard/amd/mahogany_fam10/romstage.c
View File

@ -58,14 +58,12 @@ static void post_code(u8 value) {
outb(value, 0x80);
}
#if (CONFIG_USE_FAILOVER_IMAGE == 0)
#include "arch/i386/lib/console.c"
#include "pc80/serial.c"
#include "lib/ramtest.c"
#include <cpu/amd/model_10xxx_rev.h>
#include "northbridge/amd/amdfam10/raminit.h"
#include "northbridge/amd/amdfam10/amdfam10.h"
#endif
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdfam10/reset_test.c"
@ -80,8 +78,6 @@ int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf,
#include "cpu/x86/bist.h"
#if (CONFIG_USE_FAILOVER_IMAGE == 0)
static int smbus_read_byte(u32 device, u32 address);
#include "superio/ite/it8718f/it8718f_early_serial.c"
@ -128,13 +124,10 @@ static int spd_read_byte(u32 device, u32 address)
#include "cpu/amd/model_10xxx/init_cpus.c"
#include "cpu/amd/model_10xxx/fidvid.c"
#endif /* (CONFIG_USE_FAILOVER_IMAGE == 0) */
#include "northbridge/amd/amdfam10/early_ht.c"
#include "southbridge/amd/sb700/sb700_early_setup.c"
#if (CONFIG_USE_FAILOVER_IMAGE==0)
//#include "spd_addr.h"
#include "cpu/amd/microcode/microcode.c"
#include "cpu/amd/model_10xxx/update_microcode.c"
@ -306,5 +299,3 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x43); // Should never see this post code.
}
#endif /* CONFIG_USE_FAILOVER_IMAGE==0 */

7
src/mainboard/amd/serengeti_cheetah/romstage.c
View File

@ -43,21 +43,18 @@ static void post_code(uint8_t value) {
#endif
}
#endif
#if CONFIG_USE_FAILOVER_IMAGE==0
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#include <cpu/amd/model_fxx_rev.h>
#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#endif
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#if CONFIG_USE_FAILOVER_IMAGE==0
#include "cpu/x86/bist.h"
#include "lib/delay.c"
@ -152,13 +149,10 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "cpu/amd/model_fxx/init_cpus.c"
#include "cpu/amd/model_fxx/fidvid.c"
#endif
#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
#if CONFIG_USE_FAILOVER_IMAGE==0
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr[] = {
@ -336,4 +330,3 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
}
#endif

9
src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
View File

@ -58,7 +58,6 @@ static void post_code(u8 value) {
outb(value, 0x80);
}
#if (CONFIG_USE_FAILOVER_IMAGE == 0)
#include "arch/i386/lib/console.c"
#include "pc80/serial.c"
#include "lib/ramtest.c"
@ -66,7 +65,6 @@ static void post_code(u8 value) {
#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
#include "northbridge/amd/amdfam10/raminit.h"
#include "northbridge/amd/amdfam10/amdfam10.h"
#endif
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdfam10/reset_test.c"
@ -80,8 +78,6 @@ int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf,
#include "cpu/x86/bist.h"
#if (CONFIG_USE_FAILOVER_IMAGE == 0)
#include "northbridge/amd/amdfam10/debug.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
#include "cpu/amd/mtrr/amd_earlymtrr.c"
@ -141,13 +137,10 @@ static int spd_read_byte(u32 device, u32 address)
#include "cpu/amd/model_10xxx/init_cpus.c"
#include "cpu/amd/model_10xxx/fidvid.c"
#endif /* (CONFIG_USE_FAILOVER_IMAGE == 0) */
#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
#include "northbridge/amd/amdfam10/early_ht.c"
#if (CONFIG_USE_FAILOVER_IMAGE==0)
#include "spd_addr.h"
#include "cpu/amd/microcode/microcode.c"
#include "cpu/amd/model_10xxx/update_microcode.c"
@ -316,5 +309,3 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
}
#endif /* CONFIG_USE_FAILOVER_IMAGE==0 */

6
src/mainboard/asus/a8n_e/romstage.c
View File

@ -47,8 +47,6 @@
#include "northbridge/amd/amdk8/reset_test.c"
#include "superio/ite/it8712f/it8712f_early_serial.c"
#if CONFIG_USE_FAILOVER_IMAGE == 0
/* Used by ck894_early_setup(). */
#define CK804_NUM 1
@ -96,8 +94,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/model_fxx/init_cpus.c"
#endif /* CONFIG_USE_FAILOVER_IMAGE */
#include "southbridge/nvidia/ck804/ck804_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
@ -118,7 +114,6 @@ static void sio_setup(void)
pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0xa0, dword);
}
#if CONFIG_USE_FAILOVER_IMAGE == 0
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr[] = {
@ -200,4 +195,3 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_cache_as_ram();
}
#endif /* CONFIG_USE_FAILOVER_IMAGE */

10
src/mainboard/gigabyte/ga_2761gxdk/Kconfig
View File

@ -75,16 +75,6 @@ config PCI_64BIT_PREF_MEM
default n
depends on BOARD_GIGABYTE_GA_2761GXDK
config HAVE_FALLBACK_BOOT
bool
default n
depends on BOARD_GIGABYTE_GA_2761GXDK
config USE_FALLBACK_IMAGE
bool
default n
depends on BOARD_GIGABYTE_GA_2761GXDK
config HW_MEM_HOLE_SIZEK
hex
default 0x100000

11
src/mainboard/gigabyte/ga_2761gxdk/romstage.c
View File

@ -56,7 +56,6 @@
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#if CONFIG_USE_FAILOVER_IMAGE==0
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#if CONFIG_USBDEBUG_DIRECT
@ -73,15 +72,11 @@
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
#endif
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "superio/ite/it8716f/it8716f_early_serial.c"
#include "superio/ite/it8716f/it8716f_early_init.c"
#if CONFIG_USE_FAILOVER_IMAGE==0
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/debug.c"
@ -150,8 +145,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "cpu/amd/model_fxx/fidvid.c"
#endif
#include "northbridge/amd/amdk8/early_ht.c"
@ -175,8 +168,6 @@ static void sio_setup(void)
pci_write_config32(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0xa4, dword);
}
#if CONFIG_USE_FAILOVER_IMAGE==0
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr [] = {
@ -303,5 +294,3 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
}
#endif

10
src/mainboard/gigabyte/m57sli/Kconfig
View File

@ -78,16 +78,6 @@ config PCI_64BIT_PREF_MEM
default n
depends on BOARD_GIGABYTE_M57SLI
config HAVE_FALLBACK_BOOT
bool
default n
depends on BOARD_GIGABYTE_M57SLI
config USE_FALLBACK_IMAGE
bool
default n
depends on BOARD_GIGABYTE_M57SLI
config HW_MEM_HOLE_SIZEK
hex
default 0x100000

11
src/mainboard/gigabyte/m57sli/romstage.c
View File

@ -54,7 +54,6 @@
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#if CONFIG_USE_FAILOVER_IMAGE==0
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#if CONFIG_USBDEBUG_DIRECT
@ -70,15 +69,11 @@
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
#endif
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "superio/ite/it8716f/it8716f_early_serial.c"
#include "superio/ite/it8716f/it8716f_early_init.c"
#if CONFIG_USE_FAILOVER_IMAGE==0
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/debug.c"
@ -148,8 +143,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "cpu/amd/model_fxx/fidvid.c"
#endif
#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
@ -175,8 +168,6 @@ static void sio_setup(void)
}
#if CONFIG_USE_FAILOVER_IMAGE==0
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr [] = {
@ -316,5 +307,3 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
}
#endif

10
src/mainboard/hp/dl145_g3/romstage.c
View File

@ -61,7 +61,6 @@
#include "pc80/mc146818rtc_early.c"
#if CONFIG_USE_FAILOVER_IMAGE==0
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#include "lib/ramtest.c"
@ -73,8 +72,6 @@
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
#endif
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
@ -83,8 +80,6 @@
#include "superio/nsc/pc87417/pc87417_early_serial.c"
#if CONFIG_USE_FAILOVER_IMAGE==0
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/debug.c"
@ -153,8 +148,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "cpu/amd/model_fxx/fidvid.c"
#endif
#include "northbridge/amd/amdk8/early_ht.c"
#if 0
@ -195,8 +188,6 @@ static void setup_early_ipmi_serial()
}
#endif
#if CONFIG_USE_FAILOVER_IMAGE==0
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr[] = {
@ -312,4 +303,3 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
}
#endif

2
src/mainboard/intel/d945gclf/romstage.c
View File

@ -216,9 +216,7 @@ static void early_ich7_init(void)
RCBA32(0x2034) = reg32;
}
#if CONFIG_USE_FALLBACK_IMAGE == 1
#include "southbridge/intel/i82801gx/cmos_failover.c"
#endif
#include <cbmem.h>

2
src/mainboard/intel/eagleheights/romstage.c
View File

@ -121,9 +121,7 @@ static inline int spd_read_byte(u16 device, u8 address)
#include "northbridge/intel/i3100/reset_test.c"
#include "debug.c"
#if CONFIG_USE_FALLBACK_IMAGE == 1
#include "southbridge/intel/i3100/cmos_failover.c"
#endif
void early_config(void) {
device_t dev;

8
src/mainboard/iwill/dk8_htx/romstage.c
View File

@ -32,21 +32,17 @@
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#if CONFIG_USE_FAILOVER_IMAGE==0
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#include <cpu/amd/model_fxx_rev.h>
#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#endif
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#if CONFIG_USE_FAILOVER_IMAGE==0
#include "cpu/x86/bist.h"
#include "lib/delay.c"
@ -128,13 +124,10 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "cpu/amd/model_fxx/init_cpus.c"
#include "cpu/amd/model_fxx/fidvid.c"
#endif
#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
#if CONFIG_USE_FAILOVER_IMAGE==0
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr[] = {
@ -260,4 +253,3 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
}
#endif

8
src/mainboard/iwill/dk8s2/romstage.c
View File

@ -32,21 +32,17 @@
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#if CONFIG_USE_FAILOVER_IMAGE==0
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#include <cpu/amd/model_fxx_rev.h>
#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#endif
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#if CONFIG_USE_FAILOVER_IMAGE==0
#include "cpu/x86/bist.h"
#include "lib/delay.c"
@ -128,13 +124,10 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "cpu/amd/model_fxx/init_cpus.c"
#include "cpu/amd/model_fxx/fidvid.c"
#endif
#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
#if CONFIG_USE_FAILOVER_IMAGE==0
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr[] = {
@ -260,4 +253,3 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
}
#endif

9
src/mainboard/iwill/dk8x/romstage.c
View File

@ -32,21 +32,16 @@
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#if CONFIG_USE_FAILOVER_IMAGE==0
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#include <cpu/amd/model_fxx_rev.h>
#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#endif
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#if CONFIG_USE_FAILOVER_IMAGE==0
#include "cpu/x86/bist.h"
#include "lib/delay.c"
@ -128,13 +123,10 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "cpu/amd/model_fxx/init_cpus.c"
#include "cpu/amd/model_fxx/fidvid.c"
#endif
#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
#if CONFIG_USE_FAILOVER_IMAGE==0
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr[] = {
@ -260,4 +252,3 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
}
#endif

2
src/mainboard/kontron/986lcd-m/romstage.c
View File

@ -352,9 +352,7 @@ static void early_ich7_init(void)
RCBA32(0x2034) = reg32;
}
#if CONFIG_USE_FALLBACK_IMAGE == 1
#include "southbridge/intel/i82801gx/cmos_failover.c"
#endif
#include <cbmem.h>

6
src/mainboard/msi/ms7135/romstage.c
View File

@ -47,8 +47,6 @@
#include "northbridge/amd/amdk8/reset_test.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
#if CONFIG_USE_FAILOVER_IMAGE == 0
/* Used by ck804_early_setup(). */
#define CK804_NUM 1
#define CK804_USE_NIC 1
@ -98,8 +96,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/model_fxx/init_cpus.c"
#endif /* CONFIG_USE_FAILOVER_IMAGE */
#include "southbridge/nvidia/ck804/ck804_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
@ -121,7 +117,6 @@ static void sio_setup(void)
pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0xa0, dword);
}
#if CONFIG_USE_FAILOVER_IMAGE == 0
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr[] = {
@ -204,4 +199,3 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_cache_as_ram();
}
#endif /* CONFIG_USE_FAILOVER_IMAGE */

10
src/mainboard/msi/ms7260/Kconfig
View File

@ -76,16 +76,6 @@ config PCI_64BIT_PREF_MEM
default n
depends on BOARD_MSI_MS7260
config HAVE_FALLBACK_BOOT
bool
default n
depends on BOARD_MSI_MS7260
config USE_FALLBACK_IMAGE
bool
default n
depends on BOARD_MSI_MS7260
config HW_MEM_HOLE_SIZEK
hex
default 0x100000

11
src/mainboard/msi/ms7260/romstage.c
View File

@ -58,8 +58,6 @@
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#if CONFIG_USE_FAILOVER_IMAGE == 0
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#if CONFIG_USBDEBUG_DIRECT
@ -73,15 +71,11 @@
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
#endif
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "superio/winbond/w83627ehg/w83627ehg_early_serial.c"
#include "superio/winbond/w83627ehg/w83627ehg_early_init.c"
#if CONFIG_USE_FAILOVER_IMAGE == 0
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/debug.c"
#include "cpu/amd/mtrr/amd_earlymtrr.c"
@ -129,8 +123,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
#include "cpu/amd/model_fxx/init_cpus.c"
#include "cpu/amd/model_fxx/fidvid.c"
#endif
#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
@ -152,8 +144,6 @@ static void sio_setup(void)
pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa4, dword);
}
#if CONFIG_USE_FAILOVER_IMAGE == 0
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr[] = {
@ -282,4 +272,3 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_cache_as_ram();
}
#endif

10
src/mainboard/msi/ms9282/Kconfig
View File

@ -70,16 +70,6 @@ config PCI_64BIT_PREF_MEM
default n
depends on BOARD_MSI_MS9282
config HAVE_FALLBACK_BOOT
bool
default n
depends on BOARD_MSI_MS9282
config USE_FALLBACK_IMAGE
bool
default n
depends on BOARD_MSI_MS9282
config HW_MEM_HOLE_SIZEK
hex
default 0x100000

20
src/mainboard/msi/ms9652_fam10/Kconfig
View File

@ -42,26 +42,6 @@ config CONFIG_ACPI_SSDTX_NUM
default 0x1F
depends on BOARD_MSI_MS9652_FAM10
config USE_FALLBACK_IMAGE
bool
default y
depends on BOARD_MSI_MS9652_FAM10
config HAVE_FALLBACK_BOOT
bool
default y
depends on BOARD_MSI_MS9652_FAM10
config CONFIG_USE_FAILOVER_IMAGE
bool
default y
depends on BOARD_MSI_MS9652_FAM10
config CONFIG_HAVE_FAILOVER_BOOT
bool
default y
depends on BOARD_MSI_MS9652_FAM10
config GENERATE_PIRQ_TABLE
bool
default y

10
src/mainboard/msi/ms9652_fam10/romstage.c
View File

@ -54,7 +54,6 @@ static void post_code(u8 value) {
outb(value, 0x80);
}
#if CONFIG_USE_FAILOVER_IMAGE==0
#include "arch/i386/lib/console.c"
#if CONFIG_USBDEBUG_DIRECT
#include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug_direct.c"
@ -68,14 +67,10 @@ static void post_code(u8 value) {
#include "northbridge/amd/amdfam10/raminit.h"
#include "northbridge/amd/amdfam10/amdfam10.h"
#endif
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdfam10/reset_test.c"
#include "superio/winbond/w83627ehg/w83627ehg_early_serial.c"
#if CONFIG_USE_FAILOVER_IMAGE==0
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdfam10/debug.c"
@ -143,8 +138,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "cpu/amd/model_10xxx/fidvid.c"
#endif
#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
#include "northbridge/amd/amdfam10/early_ht.c"
@ -163,7 +156,6 @@ static void sio_setup(void)
pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
}
#if CONFIG_USE_FAILOVER_IMAGE==0
#include "spd_addr.h"
#include "cpu/amd/microcode/microcode.c"
#include "cpu/amd/model_10xxx/update_microcode.c"
@ -323,5 +315,3 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x43); // Should never see this post code.
}
#endif

10
src/mainboard/nvidia/l1_2pvv/Kconfig
View File

@ -76,16 +76,6 @@ config PCI_64BIT_PREF_MEM
default n
depends on BOARD_NVIDIA_L1_2PVV
config HAVE_FALLBACK_BOOT
bool
default n
depends on BOARD_NVIDIA_L1_2PVV
config USE_FALLBACK_IMAGE
bool
default n
depends on BOARD_NVIDIA_L1_2PVV
config HW_MEM_HOLE_SIZEK
hex
default 0x100000

10
src/mainboard/nvidia/l1_2pvv/romstage.c
View File

@ -54,7 +54,6 @@
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#if CONFIG_USE_FAILOVER_IMAGE==0
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#if CONFIG_USBDEBUG_DIRECT
@ -70,15 +69,11 @@
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
#endif
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "superio/winbond/w83627ehg/w83627ehg_early_serial.c"
#include "superio/winbond/w83627ehg/w83627ehg_early_init.c"
#if CONFIG_USE_FAILOVER_IMAGE==0
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/debug.c"
@ -148,8 +143,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "cpu/amd/model_fxx/fidvid.c"
#endif
#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
@ -175,7 +168,6 @@ static void sio_setup(void)
}
#if CONFIG_USE_FAILOVER_IMAGE==0
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr [] = {
@ -301,5 +293,3 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
}
#endif

2
src/mainboard/roda/rk886ex/romstage.c
View File

@ -259,9 +259,7 @@ static void early_ich7_init(void)
RCBA32(0x2034) = reg32;
}
#if CONFIG_USE_FALLBACK_IMAGE == 1
#include "southbridge/intel/i82801gx/cmos_failover.c"
#endif
static void init_artec_dongle(void)
{

10
src/mainboard/supermicro/h8dme/romstage.c
View File

@ -52,7 +52,6 @@
// for enable the FAN
#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
#if CONFIG_USE_FAILOVER_IMAGE==0
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#include "lib/ramtest.c"
@ -64,15 +63,11 @@
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
#endif
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
#include "superio/winbond/w83627hf/w83627hf_early_init.c"
#if CONFIG_USE_FAILOVER_IMAGE==0
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/debug.c"
@ -191,8 +186,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "cpu/amd/model_fxx/fidvid.c"
#endif
#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
@ -225,8 +218,6 @@ static void sio_setup(void)
#define RC0 (2<<8)
#define RC1 (1<<8)
#if CONFIG_USE_FAILOVER_IMAGE==0
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
/* The SPD is being read from the CPU1 (marked CPU2 on the board) and we
@ -371,4 +362,3 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
}
#endif

11
src/mainboard/supermicro/h8dmr/romstage.c
View File

@ -55,7 +55,6 @@
// for enable the FAN
#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
#if CONFIG_USE_FAILOVER_IMAGE==0
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#include "lib/ramtest.c"
@ -67,15 +66,11 @@
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
#endif
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
#include "superio/winbond/w83627hf/w83627hf_early_init.c"
#if CONFIG_USE_FAILOVER_IMAGE==0
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/debug.c"
@ -137,8 +132,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "cpu/amd/model_fxx/fidvid.c"
#endif
#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
@ -167,8 +160,6 @@ static void sio_setup(void)
}
#if CONFIG_USE_FAILOVER_IMAGE==0
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr [] = {
@ -291,5 +282,3 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
}
#endif

10
src/mainboard/supermicro/h8dmr_fam10/romstage.c
View File

@ -54,7 +54,6 @@ static void post_code(u8 value) {
outb(value, 0x80);
}
#if CONFIG_USE_FAILOVER_IMAGE==0
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#include "lib/ramtest.c"
@ -65,15 +64,11 @@ static void post_code(u8 value) {
#include "northbridge/amd/amdfam10/raminit.h"
#include "northbridge/amd/amdfam10/amdfam10.h"
#endif
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdfam10/reset_test.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
#include "superio/winbond/w83627hf/w83627hf_early_init.c"
#if CONFIG_USE_FAILOVER_IMAGE==0
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdfam10/debug.c"
@ -133,8 +128,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "cpu/amd/model_10xxx/fidvid.c"
#endif
#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
#include "northbridge/amd/amdfam10/early_ht.c"
@ -163,7 +156,6 @@ static void sio_setup(void)
}
#if CONFIG_USE_FAILOVER_IMAGE==0
#include "spd_addr.h"
#include "cpu/amd/microcode/microcode.c"
#include "cpu/amd/model_10xxx/update_microcode.c"
@ -317,5 +309,3 @@ post_code(0x40);
}
#endif

10
src/mainboard/supermicro/h8qme_fam10/romstage.c
View File

@ -54,7 +54,6 @@ static void post_code(u8 value) {
outb(value, 0x80);
}
#if CONFIG_USE_FAILOVER_IMAGE==0
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#include "lib/ramtest.c"
@ -65,15 +64,11 @@ static void post_code(u8 value) {
#include "northbridge/amd/amdfam10/raminit.h"
#include "northbridge/amd/amdfam10/amdfam10.h"
#endif
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdfam10/reset_test.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
#include "superio/winbond/w83627hf/w83627hf_early_init.c"
#if CONFIG_USE_FAILOVER_IMAGE==0
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdfam10/debug.c"
@ -136,8 +131,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "cpu/amd/model_10xxx/fidvid.c"
#endif
#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
#include "northbridge/amd/amdfam10/early_ht.c"
@ -166,7 +159,6 @@ static void sio_setup(void)
}
#if CONFIG_USE_FAILOVER_IMAGE==0
#include "spd_addr.h"
#include "cpu/amd/microcode/microcode.c"
#include "cpu/amd/model_10xxx/update_microcode.c"
@ -360,5 +352,3 @@ post_code(0x40);
}
#endif

10
src/mainboard/tyan/s2895/romstage.c
View File

@ -19,7 +19,6 @@
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#if CONFIG_USE_FAILOVER_IMAGE==0
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#include "lib/ramtest.c"
@ -32,8 +31,6 @@
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
#endif
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "superio/smsc/lpc47b397/lpc47b397_early_serial.c"
@ -42,8 +39,6 @@
#define SUPERIO_GPIO_IO_BASE 0x400
#if CONFIG_USE_FAILOVER_IMAGE==0
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/debug.c"
@ -114,8 +109,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "cpu/amd/model_fxx/init_cpus.c"
#endif
#include "southbridge/nvidia/ck804/ck804_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
@ -147,8 +140,6 @@ static void sio_setup(void)
}
#if CONFIG_USE_FAILOVER_IMAGE==0
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr [] = {
@ -226,4 +217,3 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_cache_as_ram();
}
#endif

10
src/mainboard/tyan/s2912/Kconfig
View File

@ -76,16 +76,6 @@ config PCI_64BIT_PREF_MEM
default n
depends on BOARD_TYAN_S2912
config HAVE_FALLBACK_BOOT
bool
default n
depends on BOARD_TYAN_S2912
config USE_FALLBACK_IMAGE
bool
default n
depends on BOARD_TYAN_S2912
config HW_MEM_HOLE_SIZEK
hex
default 0x100000

11
src/mainboard/tyan/s2912/romstage.c
View File

@ -54,7 +54,6 @@
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#if CONFIG_USE_FAILOVER_IMAGE==0
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#if CONFIG_USBDEBUG_DIRECT
@ -70,15 +69,11 @@
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
#endif
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
#include "superio/winbond/w83627hf/w83627hf_early_init.c"
#if CONFIG_USE_FAILOVER_IMAGE==0
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/debug.c"
@ -146,8 +141,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "cpu/amd/model_fxx/fidvid.c"
#endif
#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
@ -174,8 +167,6 @@ static void sio_setup(void)
}
#if CONFIG_USE_FAILOVER_IMAGE==0
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr [] = {
@ -299,5 +290,3 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
}
#endif

30
src/mainboard/tyan/s2912_fam10/Kconfig
View File

@ -38,26 +38,6 @@ config DCACHE_RAM_GLOBAL_VAR_SIZE
default 0x04000
depends on BOARD_TYAN_S2912_FAM10
config USE_FALLBACK_IMAGE
bool
default y
depends on BOARD_TYAN_S2912_FAM10
config HAVE_FALLBACK_BOOT
bool
default y
depends on BOARD_TYAN_S2912_FAM10
config CONFIG_USE_FAILOVER_IMAGE
bool
default y
depends on BOARD_TYAN_S2912_FAM10
config CONFIG_HAVE_FAILOVER_BOOT
bool
default y
depends on BOARD_TYAN_S2912_FAM10
config APIC_ID_OFFSET
hex
default 0
@ -98,16 +78,6 @@ config PCI_64BIT_PREF_MEM
default n
depends on BOARD_TYAN_S2912_FAM10
config HAVE_FALLBACK_BOOT
bool
default n
depends on BOARD_TYAN_S2912_FAM10
config USE_FALLBACK_IMAGE
bool
default n
depends on BOARD_TYAN_S2912_FAM10
config HW_MEM_HOLE_SIZEK
hex
default 0x100000

10
src/mainboard/tyan/s2912_fam10/romstage.c
View File

@ -53,7 +53,6 @@ static void post_code(u8 value) {
outb(value, 0x80);
}
#if CONFIG_USE_FAILOVER_IMAGE==0
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#if CONFIG_USBDEBUG_DIRECT
@ -68,15 +67,11 @@ static void post_code(u8 value) {
#include "northbridge/amd/amdfam10/raminit.h"
#include "northbridge/amd/amdfam10/amdfam10.h"
#endif
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdfam10/reset_test.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
#include "superio/winbond/w83627hf/w83627hf_early_init.c"
#if CONFIG_USE_FAILOVER_IMAGE==0
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdfam10/debug.c"
@ -142,8 +137,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "cpu/amd/model_10xxx/fidvid.c"
#endif
#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
#include "northbridge/amd/amdfam10/early_ht.c"
@ -168,7 +161,6 @@ static void sio_setup(void)
}
#if CONFIG_USE_FAILOVER_IMAGE==0
#include "spd_addr.h"
#include "cpu/amd/microcode/microcode.c"
#include "cpu/amd/model_10xxx/update_microcode.c"
@ -317,5 +309,3 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x43); // Should never see this post code.
}
#endif

4
src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c
View File

@ -3,8 +3,6 @@
* by yinghai.lu@amd.com
*/
#if CONFIG_USE_FALLBACK_IMAGE == 1
static void bcm5785_enable_rom(void)
{
unsigned char byte;
@ -42,8 +40,6 @@ static void bcm5785_enable_lpc(void)
byte |=(1<<1)|(1<<0);
pci_write_config8(dev, 0x48, byte);
}
#endif /* CONFIG_USE_FALLBACK_IMAGE == 1 */
static void bcm5785_enable_wdt_port_cf9(void)
{