soc/mediatek/mt8188: Fix AP hang when enabling cpufreq-hw driver

When enabling cpufreq-hw driver, it is required for MCUPM to access
secure registers. Therefore, we enable side-band to allow MCUPM to
access the secure registers.

BUG=b:236331463
TEST=It works well after boot to login shell.

Change-Id: I67b08c38a31a7eae1bc59543a5148a78b61456d6
Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69088
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
This commit is contained in:
Liju-Clr Chen 2022-11-01 13:14:13 +08:00 committed by Felix Held
parent 0feb5ce0c8
commit 78b7fb2c17
2 changed files with 6 additions and 1 deletions

View File

@ -1550,7 +1550,10 @@ static void dump_peri_par_ao_apc(uintptr_t base)
static void infra_init(uintptr_t base) static void infra_init(uintptr_t base)
{ {
/* Default APC setting */ /* Side-band */
SET32_BITFIELDS(getreg(base, MAS_SEC_0), MCUPM_SEC, SECURE_TRANS);
/* TODO: Setup SCP, SSPM and MCUPM permissions in APC . */
set_infra_ao_apc(base); set_infra_ao_apc(base);
} }

View File

@ -17,6 +17,8 @@ enum devapc_ao_offset {
AO_APC_CON = 0x00F00, AO_APC_CON = 0x00F00,
}; };
DEFINE_BIT(MCUPM_SEC, 1)
/****************************************************************************** /******************************************************************************
* STRUCTURE DEFINITION * STRUCTURE DEFINITION
******************************************************************************/ ******************************************************************************/