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setup for v2 

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1278 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Greg Watson 2003-11-15 15:04:58 +00:00
parent d4718ff415
commit 78c19a11eb
1 changed files with 18 additions and 31 deletions
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49
targets/motorola/sandpoint/Config.lb
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@ -19,17 +19,18 @@ uses UART0_IO_BASE
uses CONFIG_IDE_STREAM uses CONFIG_IDE_STREAM
uses IDE_BOOT_DRIVE uses IDE_BOOT_DRIVE
uses IDE_SWAB IDE_OFFSET uses IDE_SWAB IDE_OFFSET
uses ROM_SIZE ROM_IMAGE_SIZE uses ROM_SIZE
uses ROM_SECTION_SIZE
uses ROM_SECTION_OFFSET
uses _RESET uses _RESET
uses _EXCEPTION_VECTORS uses _EXCEPTION_VECTORS
uses _ROMBASE uses _ROMBASE
uses _ROMSTART
uses _RAMBASE uses _RAMBASE
uses STACK_SIZE HEAP_SIZE uses _RAMSTART
uses STACK_SIZE
uses HEAP_SIZE
## use a cross compiler ## use a cross compiler
option CROSS_COMPILE="powerpc-eabi-" #option CROSS_COMPILE="powerpc-eabi-"
#option CROSS_COMPILE="ppc_74xx-" #option CROSS_COMPILE="ppc_74xx-"
## Use stage 1 initialization code ## Use stage 1 initialization code
@ -44,8 +45,8 @@ option NO_POST=1
## Enable serial console ## Enable serial console
option DEFAULT_CONSOLE_LOGLEVEL=8 option DEFAULT_CONSOLE_LOGLEVEL=8
option CONFIG_CONSOLE_SERIAL8250=1 option CONFIG_CONSOLE_SERIAL8250=1
option TTYS0_BASE=0x3f0 option UART0_IO_BASE=0x3f0
option UART0_IO_BASE=0xfe000000+TTYS0_BASE option TTYS0_BASE=0xfe000000+UART0_IO_BASE
## Boot linux from IDE ## Boot linux from IDE
option CONFIG_IDE_STREAM=1 option CONFIG_IDE_STREAM=1
@ -53,46 +54,32 @@ option IDE_BOOT_DRIVE=0
option IDE_SWAB=1 option IDE_SWAB=1
option IDE_OFFSET=0 option IDE_OFFSET=0
# ROM is 1Mb
option ROM_SIZE=1048576 option ROM_SIZE=1048576
## For the trick of using cache as ram # Set stack and heap sizes (stage 2)
## put the fake ram location at this address
#option CACHE_RAM_BASE=0x00200000
#option CACHE_RAM_SIZE=0x00004000
##
## Use a 64K stack
##
option STACK_SIZE=0x10000 option STACK_SIZE=0x10000
##
## Use a 64K heap
##
option HEAP_SIZE=0x10000 option HEAP_SIZE=0x10000
## Compute the location and size of where this firmware image
## (linuxBIOS plus bootloader) will live in the boot rom chip.
##
option ROM_SECTION_SIZE=ROM_SIZE
option ROM_SECTION_OFFSET=0
# Sandpoint Demo Board # Sandpoint Demo Board
romimage "normal" romimage "normal"
## Sandpoint reset vector ## Base of ROM
option _RESET=0xfff00100 option _ROMBASE=0xfff00000
## Excpetoion vectors ## Sandpoint reset vector
option _RESET=_ROMBASE+0x100
## Exception vectors (other than reset vector)
option _EXCEPTION_VECTORS=_RESET+0x100 option _EXCEPTION_VECTORS=_RESET+0x100
## Start of linuxBIOS in the boot rom ## Start of linuxBIOS in the boot rom
## = _RESET + exeception vector table size ## = _RESET + exeception vector table size
option _ROMBASE=0xfff03100 option _ROMSTART=_RESET+0x3100
## LinuxBIOS C code runs at this location in RAM ## LinuxBIOS C code runs at this location in RAM
option _RAMBASE=0x00100000 option _RAMBASE=0x00100000
option _RAMSTART=0x00100000
## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
option ROM_IMAGE_SIZE=49152
option CONFIG_SANDPOINT_ALTIMUS=1 option CONFIG_SANDPOINT_ALTIMUS=1
mainboard motorola/sandpoint mainboard motorola/sandpoint