ACPI: Add acpi_is_wakeup_s3() for romstage

This replaces acpi_is_wakeup_early().

Change-Id: I23112c1fc7b6f99584bc065fbf6b10fb073b1eb6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8187
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
This commit is contained in:
Kyösti Mälkki 2015-01-09 23:48:47 +02:00
parent 2320cbebc6
commit 78c5d584a0
36 changed files with 177 additions and 206 deletions

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@ -581,14 +581,21 @@ static inline int acpi_s3_resume_allowed(void)
#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) #if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
extern int acpi_slp_type; extern int acpi_slp_type;
#ifdef __PRE_RAM__
static inline int acpi_is_wakeup_s3(void)
{
return (acpi_get_sleep_type() == 3);
}
#else
int acpi_is_wakeup(void); int acpi_is_wakeup(void);
int acpi_is_wakeup_s3(void); int acpi_is_wakeup_s3(void);
int acpi_is_wakeup_early(void); #endif
#else #else
#define acpi_slp_type 0 #define acpi_slp_type 0
static inline int acpi_is_wakeup(void) { return 0; } static inline int acpi_is_wakeup(void) { return 0; }
static inline int acpi_is_wakeup_s3(void) { return 0; } static inline int acpi_is_wakeup_s3(void) { return 0; }
static inline int acpi_is_wakeup_early(void) { return 0; }
#endif #endif
#endif /* __ASM_ACPI_H */ #endif /* __ASM_ACPI_H */

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@ -12,13 +12,11 @@ UINT32 GetHeapBase(AMD_CONFIG_PARAMS *StdHeader)
{ {
UINT32 heap = BIOS_HEAP_START_ADDRESS; UINT32 heap = BIOS_HEAP_START_ADDRESS;
#if CONFIG_HAVE_ACPI_RESUME if (acpi_is_wakeup_s3())
/* Both romstage and ramstage has this S3 detect. */
if (acpi_get_sleep_type() == 3)
heap = (UINT32) cbmem_find(CBMEM_ID_RESUME_SCRATCH) + heap = (UINT32) cbmem_find(CBMEM_ID_RESUME_SCRATCH) +
(CONFIG_HIGH_SCRATCH_MEMORY_SIZE - BIOS_HEAP_SIZE); (CONFIG_HIGH_SCRATCH_MEMORY_SIZE - BIOS_HEAP_SIZE);
/* himem_heap_base + high_stack_size */ /* himem_heap_base + high_stack_size */
#endif
return heap; return heap;
} }

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@ -101,12 +101,10 @@ void post_cache_as_ram(void)
{ {
void *resume_backup_memory = NULL; void *resume_backup_memory = NULL;
int s3resume = acpi_s3_resume_allowed() && acpi_is_wakeup_early(); int s3resume = acpi_is_wakeup_s3();
if (s3resume) { if (s3resume) {
#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
cbmem_recovery(s3resume); cbmem_recovery(s3resume);
resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); resume_backup_memory = cbmem_find(CBMEM_ID_RESUME);
#endif
} }
prepare_romstage_ramstack(resume_backup_memory); prepare_romstage_ramstack(resume_backup_memory);
@ -141,10 +139,8 @@ void cache_as_ram_new_stack (void)
set_var_mtrr(0, 0x00000000, CONFIG_RAMTOP, MTRR_TYPE_WRBACK); set_var_mtrr(0, 0x00000000, CONFIG_RAMTOP, MTRR_TYPE_WRBACK);
enable_cache(); enable_cache();
if (acpi_s3_resume_allowed() && acpi_is_wakeup_early()) { if (acpi_is_wakeup_s3()) {
#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); resume_backup_memory = cbmem_find(CBMEM_ID_RESUME);
#endif
} }
prepare_ramstage_region(resume_backup_memory); prepare_ramstage_region(resume_backup_memory);

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@ -87,7 +87,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x39); post_code(0x39);
agesawrapper_amdinitearly(); agesawrapper_amdinitearly();
int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); int s3resume = acpi_is_wakeup_s3();
if (!s3resume) { if (!s3resume) {
post_code(0x40); post_code(0x40);
agesawrapper_amdinitpost(); agesawrapper_amdinitpost();

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@ -90,7 +90,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x39); post_code(0x39);
AGESAWRAPPER(amdinitearly); AGESAWRAPPER(amdinitearly);
int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); int s3resume = acpi_is_wakeup_s3();
if (!s3resume) { if (!s3resume) {
post_code(0x40); post_code(0x40);
AGESAWRAPPER(amdinitpost); AGESAWRAPPER(amdinitpost);

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@ -71,7 +71,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x39); post_code(0x39);
agesawrapper_amdinitearly(); agesawrapper_amdinitearly();
int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); int s3resume = acpi_is_wakeup_s3();
if (!s3resume) { if (!s3resume) {
post_code(0x40); post_code(0x40);
agesawrapper_amdinitpost(); agesawrapper_amdinitpost();

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@ -86,7 +86,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x39); post_code(0x39);
agesawrapper_amdinitearly(); agesawrapper_amdinitearly();
int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); int s3resume = acpi_is_wakeup_s3();
if (!s3resume) { if (!s3resume) {
post_code(0x40); post_code(0x40);
agesawrapper_amdinitpost(); agesawrapper_amdinitpost();

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@ -85,7 +85,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x39); post_code(0x39);
agesawrapper_amdinitearly(); agesawrapper_amdinitearly();
int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); int s3resume = acpi_is_wakeup_s3();
if (!s3resume) { if (!s3resume) {
post_code(0x40); post_code(0x40);
agesawrapper_amdinitpost(); agesawrapper_amdinitpost();

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@ -111,7 +111,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x39); post_code(0x39);
agesawrapper_amdinitearly(); agesawrapper_amdinitearly();
int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); int s3resume = acpi_is_wakeup_s3();
if (!s3resume) { if (!s3resume) {
post_code(0x40); post_code(0x40);
agesawrapper_amdinitpost(); agesawrapper_amdinitpost();

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@ -131,7 +131,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x39); post_code(0x39);
agesawrapper_amdinitearly(); agesawrapper_amdinitearly();
int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); int s3resume = acpi_is_wakeup_s3();
if (!s3resume) { if (!s3resume) {
post_code(0x40); post_code(0x40);
agesawrapper_amdinitpost(); agesawrapper_amdinitpost();

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@ -94,7 +94,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x39); post_code(0x39);
agesawrapper_amdinitearly(); agesawrapper_amdinitearly();
int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); int s3resume = acpi_is_wakeup_s3();
if (!s3resume) { if (!s3resume) {
post_code(0x40); post_code(0x40);
agesawrapper_amdinitpost(); agesawrapper_amdinitpost();

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@ -87,7 +87,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x39); post_code(0x39);
agesawrapper_amdinitearly(); agesawrapper_amdinitearly();
int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); int s3resume = acpi_is_wakeup_s3();
if (!s3resume) { if (!s3resume) {
post_code(0x40); post_code(0x40);
agesawrapper_amdinitpost(); agesawrapper_amdinitpost();

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@ -100,7 +100,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x39); post_code(0x39);
agesawrapper_amdinitearly(); agesawrapper_amdinitearly();
int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); int s3resume = acpi_is_wakeup_s3();
if (!s3resume) { if (!s3resume) {
post_code(0x40); post_code(0x40);
agesawrapper_amdinitpost(); agesawrapper_amdinitpost();

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@ -63,7 +63,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x39); post_code(0x39);
agesawrapper_amdinitearly(); agesawrapper_amdinitearly();
int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); int s3resume = acpi_is_wakeup_s3();
if (!s3resume) { if (!s3resume) {
post_code(0x40); post_code(0x40);
agesawrapper_amdinitpost(); agesawrapper_amdinitpost();

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@ -102,7 +102,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x39); post_code(0x39);
agesawrapper_amdinitearly(); agesawrapper_amdinitearly();
int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); int s3resume = acpi_is_wakeup_s3();
if (!s3resume) { if (!s3resume) {
post_code(0x40); post_code(0x40);
agesawrapper_amdinitpost(); agesawrapper_amdinitpost();

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@ -63,7 +63,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x39); post_code(0x39);
agesawrapper_amdinitearly(); agesawrapper_amdinitearly();
int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); int s3resume = acpi_is_wakeup_s3();
if (!s3resume) { if (!s3resume) {
post_code(0x40); post_code(0x40);
agesawrapper_amdinitpost(); agesawrapper_amdinitpost();

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@ -85,7 +85,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x39); post_code(0x39);
agesawrapper_amdinitearly(); agesawrapper_amdinitearly();
int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); int s3resume = acpi_is_wakeup_s3();
if (!s3resume) { if (!s3resume) {
post_code(0x40); post_code(0x40);
/* Reboots with outb(3,0x92), outb(4,0xcf9) or triple-fault all /* Reboots with outb(3,0x92), outb(4,0xcf9) or triple-fault all

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@ -86,7 +86,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x39); post_code(0x39);
agesawrapper_amdinitearly(); agesawrapper_amdinitearly();
int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); int s3resume = acpi_is_wakeup_s3();
if (!s3resume) { if (!s3resume) {
post_code(0x40); post_code(0x40);
/* Reboots with outb(3,0x92), outb(4,0xcf9) or triple-fault all /* Reboots with outb(3,0x92), outb(4,0xcf9) or triple-fault all

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@ -2349,11 +2349,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
{ {
int i; int i;
u32 whatWait = 0; u32 whatWait = 0;
#if CONFIG_HAVE_ACPI_RESUME int suspend = acpi_is_wakeup_s3();
int suspend = acpi_is_wakeup_early();
#else
int suspend = 0;
#endif
/* Error if I don't have memory */ /* Error if I don't have memory */
if (memory_end_k(ctrl, controllers) == 0) { if (memory_end_k(ctrl, controllers) == 0) {

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@ -26,6 +26,7 @@
#include <cpu/amd/mtrr.h> #include <cpu/amd/mtrr.h>
#include <stdlib.h> #include <stdlib.h>
#include <arch/acpi.h>
#include "raminit.h" #include "raminit.h"
#include "f.h" #include "f.h"
#include <spd_ddr2.h> #include <spd_ddr2.h>
@ -3017,11 +3018,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl,
struct sys_info *sysinfo) struct sys_info *sysinfo)
{ {
int i; int i;
#if CONFIG_HAVE_ACPI_RESUME int suspend = acpi_is_wakeup_s3();
int suspend = acpi_is_wakeup_early();
#else
int suspend = 0;
#endif
#if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1 #if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1
unsigned cpu_f0_f1[8]; unsigned cpu_f0_f1[8];

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@ -19,7 +19,9 @@ ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c
romstage-y += early_setup.c romstage-y += early_setup.c
ramstage-$(CONFIG_SPI_FLASH) += spi.c ramstage-$(CONFIG_SPI_FLASH) += spi.c
ramstage-y += resume.c ramstage-y += resume.c ramtop.c
romstage-y += ramtop.c
romstage-y += imc.c romstage-y += imc.c
ramstage-y += imc.c ramstage-y += imc.c

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@ -123,32 +123,4 @@ int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos)
return nvram_pos; return nvram_pos;
} }
#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
int acpi_get_sleep_type(void)
{
u16 tmp = inw(ACPI_PM1_CNT_BLK);
tmp = ((tmp & (7 << 10)) >> 10);
/* printk(BIOS_DEBUG, "SLP_TYP type was %x\n", tmp); */
return (int)tmp;
}
int acpi_is_wakeup_early(void)
{
return (acpi_get_sleep_type() == 3);
}
#endif /* CONFIG_HAVE_ACPI_RESUME */
unsigned long get_top_of_ram(void)
{
uint32_t xdata = 0;
int xnvram_pos = 0xf8, xi;
for (xi = 0; xi<4; xi++) {
outb(xnvram_pos, BIOSRAM_INDEX);
xdata &= ~(0xff << (xi * 8));
xdata |= inb(BIOSRAM_DATA) << (xi *8);
xnvram_pos++;
}
return (unsigned long) xdata;
}
#endif /* _HUDSON_EARLY_SETUP_C_ */ #endif /* _HUDSON_EARLY_SETUP_C_ */

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@ -38,30 +38,6 @@
*/ */
#define PM_MMIO_BASE 0xfed80300 #define PM_MMIO_BASE 0xfed80300
#if CONFIG_HAVE_ACPI_RESUME
int acpi_get_sleep_type(void)
{
u16 tmp = inw(ACPI_PM1_CNT_BLK);
tmp = ((tmp & (7 << 10)) >> 10);
/* printk(BIOS_DEBUG, "SLP_TYP type was %x\n", tmp); */
return (int)tmp;
}
#endif
void backup_top_of_ram(uint64_t ramtop)
{
u32 dword = (u32) ramtop;
int nvram_pos = 0xf8, i; /* temp */
/* printk(BIOS_DEBUG, "dword=%x\n", dword); */
for (i = 0; i<4; i++) {
/* printk(BIOS_DEBUG, "nvram_pos=%x, dword>>(8*i)=%x\n", nvram_pos, (dword >>(8 * i)) & 0xff); */
outb(nvram_pos, BIOSRAM_INDEX);
outb((dword >>(8 * i)) & 0xff , BIOSRAM_DATA);
nvram_pos++;
}
}
void pm_write8(u8 reg, u8 value) void pm_write8(u8 reg, u8 value)
{ {
write8(PM_MMIO_BASE + reg, value); write8(PM_MMIO_BASE + reg, value);
@ -160,22 +136,6 @@ void hudson_enable(device_t dev)
} }
} }
#if CONFIG_HAVE_ACPI_RESUME
unsigned long get_top_of_ram(void)
{
uint32_t xdata = 0;
int xnvram_pos = 0xf8, xi;
if (acpi_get_sleep_type() != 3)
return 0;
for (xi = 0; xi<4; xi++) {
outb(xnvram_pos, BIOSRAM_INDEX);
xdata &= ~(0xff << (xi * 8));
xdata |= inb(BIOSRAM_DATA) << (xi *8);
xnvram_pos++;
}
return (unsigned long) xdata;
}
#endif
static void hudson_init_acpi_ports(void) static void hudson_init_acpi_ports(void)
{ {

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@ -0,0 +1,59 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2010 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <stdint.h>
#include <arch/io.h>
#include <arch/acpi.h>
#include <cbmem.h>
#include "hudson.h"
int acpi_get_sleep_type(void)
{
u16 tmp = inw(ACPI_PM1_CNT_BLK);
tmp = ((tmp & (7 << 10)) >> 10);
return (int)tmp;
}
#ifndef __PRE_RAM__
void backup_top_of_ram(uint64_t ramtop)
{
u32 dword = (u32) ramtop;
int nvram_pos = 0xf8, i; /* temp */
for (i = 0; i<4; i++) {
outb(nvram_pos, BIOSRAM_INDEX);
outb((dword >>(8 * i)) & 0xff , BIOSRAM_DATA);
nvram_pos++;
}
}
#endif
unsigned long get_top_of_ram(void)
{
uint32_t xdata = 0;
int xnvram_pos = 0xf8, xi;
if (acpi_get_sleep_type() != 3)
return 0;
for (xi = 0; xi<4; xi++) {
outb(xnvram_pos, BIOSRAM_INDEX);
xdata &= ~(0xff << (xi * 8));
xdata |= inb(BIOSRAM_DATA) << (xi *8);
xnvram_pos++;
}
return (unsigned long) xdata;
}

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@ -34,6 +34,9 @@ ramstage-$(CONFIG_SB800_IMC_FAN_CONTROL) += fan.c
ramstage-$(CONFIG_SPI_FLASH) += spi.c ramstage-$(CONFIG_SPI_FLASH) += spi.c
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c
romstage-$(CONFIG_HAVE_ACPI_RESUME) += ramtop.c
ramstage-$(CONFIG_HAVE_ACPI_RESUME) += ramtop.c
romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += ../../sb800/enable_usbdebug.c romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += ../../sb800/enable_usbdebug.c
ramstage-$(CONFIG_USBDEBUG) += ../../sb800/enable_usbdebug.c ramstage-$(CONFIG_USBDEBUG) += ../../sb800/enable_usbdebug.c

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@ -26,48 +26,6 @@
#include <arch/io.h> #include <arch/io.h>
#include <arch/acpi.h> #include <arch/acpi.h>
#if CONFIG_HAVE_ACPI_RESUME
int acpi_get_sleep_type(void)
{
u16 tmp = inw(PM1_CNT_BLK_ADDRESS);
tmp = ((tmp & (7 << 10)) >> 10);
/* printk(BIOS_DEBUG, "SLP_TYP type was %x\n", tmp); */
return (int)tmp;
}
#endif
#ifndef __PRE_RAM__
void backup_top_of_ram(uint64_t ramtop)
{
u32 dword = (u32) ramtop;
int nvram_pos = 0xf8, i; /* temp */
printk(BIOS_DEBUG, "dword=%x\n", dword);
for (i = 0; i<4; i++) {
printk(BIOS_DEBUG, "nvram_pos=%x, dword>>(8*i)=%x\n", nvram_pos, (dword >>(8 * i)) & 0xff);
outb(nvram_pos, BIOSRAM_INDEX);
outb((dword >>(8 * i)) & 0xff , BIOSRAM_DATA);
nvram_pos++;
}
}
#endif
#if CONFIG_HAVE_ACPI_RESUME
unsigned long get_top_of_ram(void)
{
u32 xdata = 0;
int xnvram_pos = 0xf8, xi;
if (acpi_get_sleep_type() != 3)
return 0;
for (xi = 0; xi<4; xi++) {
outb(xnvram_pos, BIOSRAM_INDEX);
xdata &= ~(0xff << (xi * 8));
xdata |= inb(BIOSRAM_DATA) << (xi *8);
xnvram_pos++;
}
return (unsigned long) xdata;
}
#endif
/** /**
* @brief South Bridge CIMx configuration * @brief South Bridge CIMx configuration
* *
@ -80,10 +38,7 @@ void sb800_cimx_config(AMDSBCFG *sb_config)
if (!sb_config) if (!sb_config)
return; return;
#if CONFIG_HAVE_ACPI_RESUME sb_config->S3Resume = acpi_is_wakeup_s3();
if (acpi_get_sleep_type() == 3)
sb_config->S3Resume = 1;
#endif
/* header */ /* header */
sb_config->StdHeader.PcieBasePtr = PCIEX_BASE_ADDRESS; sb_config->StdHeader.PcieBasePtr = PCIEX_BASE_ADDRESS;

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@ -20,7 +20,6 @@
#include <stdint.h> #include <stdint.h>
#include <device/pci_ids.h> #include <device/pci_ids.h>
#include <arch/io.h> /* inl, outl */ #include <arch/io.h> /* inl, outl */
#include <arch/acpi.h>
#include "SBPLATFORM.h" #include "SBPLATFORM.h"
#include "sb_cimx.h" #include "sb_cimx.h"
#include "cfg.h" /*sb800_cimx_config*/ #include "cfg.h" /*sb800_cimx_config*/
@ -74,10 +73,3 @@ void sb800_clk_output_48Mhz(void)
*(volatile u32 *)(ACPI_MMIO_BASE + MISC_BASE + 0x40) &= ~((1 << 0) | (1 << 2)); /* 48Mhz */ *(volatile u32 *)(ACPI_MMIO_BASE + MISC_BASE + 0x40) &= ~((1 << 0) | (1 << 2)); /* 48Mhz */
*(volatile u32 *)(ACPI_MMIO_BASE + MISC_BASE + 0x40) |= 1 << 1; /* 48Mhz */ *(volatile u32 *)(ACPI_MMIO_BASE + MISC_BASE + 0x40) |= 1 << 1; /* 48Mhz */
} }
#if CONFIG_HAVE_ACPI_RESUME
int acpi_is_wakeup_early(void)
{
return (acpi_get_sleep_type() == 3);
}
#endif

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@ -0,0 +1,59 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2010 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <stdint.h>
#include <arch/io.h>
#include <arch/acpi.h>
#include <cbmem.h>
#include "SBPLATFORM.h"
int acpi_get_sleep_type(void)
{
u16 tmp = inw(PM1_CNT_BLK_ADDRESS);
tmp = ((tmp & (7 << 10)) >> 10);
return (int)tmp;
}
#ifndef __PRE_RAM__
void backup_top_of_ram(uint64_t ramtop)
{
u32 dword = (u32) ramtop;
int nvram_pos = 0xf8, i; /* temp */
for (i = 0; i<4; i++) {
outb(nvram_pos, BIOSRAM_INDEX);
outb((dword >>(8 * i)) & 0xff , BIOSRAM_DATA);
nvram_pos++;
}
}
#endif
unsigned long get_top_of_ram(void)
{
u32 xdata = 0;
int xnvram_pos = 0xf8, xi;
if (acpi_get_sleep_type() != 3)
return 0;
for (xi = 0; xi<4; xi++) {
outb(xnvram_pos, BIOSRAM_INDEX);
xdata &= ~(0xff << (xi * 8));
xdata |= inb(BIOSRAM_DATA) << (xi *8);
xnvram_pos++;
}
return (unsigned long) xdata;
}

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@ -721,20 +721,18 @@ int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos)
return nvram_pos; return nvram_pos;
} }
#if CONFIG_HAVE_ACPI_RESUME int acpi_get_sleep_type(void)
int acpi_is_wakeup_early(void)
{ {
u16 tmp; u16 tmp;
tmp = inw(ACPI_PM1_CNT_BLK); tmp = inw(ACPI_PM1_CNT_BLK);
printk(BIOS_DEBUG, "IN TEST WAKEUP %x\n", tmp); return ((tmp & (7 << 10)) >> 10);
return (((tmp & (7 << 10)) >> 10) == 3);
} }
unsigned long get_top_of_ram(void) unsigned long get_top_of_ram(void)
{ {
uint32_t xdata = 0; uint32_t xdata = 0;
int xnvram_pos = 0xfc, xi; int xnvram_pos = 0xfc, xi;
if (!acpi_is_wakeup_early()) if (acpi_get_sleep_type() != 3)
return 0; return 0;
for (xi = 0; xi<4; xi++) { for (xi = 0; xi<4; xi++) {
outb(xnvram_pos, BIOSRAM_INDEX); outb(xnvram_pos, BIOSRAM_INDEX);
@ -744,6 +742,5 @@ unsigned long get_top_of_ram(void)
} }
return (unsigned long) xdata; return (unsigned long) xdata;
} }
#endif
#endif #endif

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@ -29,7 +29,6 @@
#include <pc80/isa-dma.h> #include <pc80/isa-dma.h>
#include <arch/io.h> #include <arch/io.h>
#include <arch/ioapic.h> #include <arch/ioapic.h>
#include <arch/acpi.h>
#include <cbmem.h> #include <cbmem.h>
#include <cpu/amd/powernow.h> #include <cpu/amd/powernow.h>
#include "sb700.h" #include "sb700.h"
@ -80,19 +79,15 @@ static void lpc_init(device_t dev)
#endif #endif
pci_write_config8(dev, 0x78, byte); pci_write_config8(dev, 0x78, byte);
/* hack, but the whole sb700 startup lacks any device which
is doing the acpi init */
#if CONFIG_HAVE_ACPI_RESUME
{
u16 tmp = inw(ACPI_PM1_CNT_BLK);
acpi_slp_type = ((tmp & (7 << 10)) >> 10);
printk(BIOS_DEBUG, "SLP_TYP type was %x\n", acpi_slp_type);
}
#endif
cmos_check_update_date(); cmos_check_update_date();
} }
int acpi_get_sleep_type(void)
{
u16 tmp = inw(ACPI_PM1_CNT_BLK);
return ((tmp & (7 << 10)) >> 10);
}
void backup_top_of_ram(uint64_t ramtop) void backup_top_of_ram(uint64_t ramtop)
{ {
u32 dword = (u32) ramtop; u32 dword = (u32) ramtop;

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@ -666,20 +666,18 @@ int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos)
return nvram_pos; return nvram_pos;
} }
#if CONFIG_HAVE_ACPI_RESUME int acpi_get_sleep_type(void)
int acpi_is_wakeup_early(void)
{ {
u16 tmp; u16 tmp;
tmp = inw(ACPI_PM1_CNT_BLK); tmp = inw(ACPI_PM1_CNT_BLK);
printk(BIOS_DEBUG, "IN TEST WAKEUP %x\n", tmp); return ((tmp & (7 << 10)) >> 10);
return (((tmp & (7 << 10)) >> 10) == 3);
} }
unsigned long get_top_of_ram(void) unsigned long get_top_of_ram(void)
{ {
uint32_t xdata = 0; uint32_t xdata = 0;
int xnvram_pos = 0xfc, xi; int xnvram_pos = 0xfc, xi;
if (!acpi_is_wakeup_early()) if (acpi_get_sleep_type() != 3)
return 0; return 0;
for (xi = 0; xi<4; xi++) { for (xi = 0; xi<4; xi++) {
outb(xnvram_pos, BIOSRAM_INDEX); outb(xnvram_pos, BIOSRAM_INDEX);
@ -689,6 +687,5 @@ unsigned long get_top_of_ram(void)
} }
return (unsigned long) xdata; return (unsigned long) xdata;
} }
#endif
#endif #endif

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@ -31,11 +31,6 @@
#include "i82371eb.h" #include "i82371eb.h"
#include "smbus.h" #include "smbus.h"
#if CONFIG_HAVE_ACPI_RESUME
extern u8 acpi_slp_type;
int acpi_get_sleep_type(void);
#endif
static void pwrmgt_enable(struct device *dev) static void pwrmgt_enable(struct device *dev)
{ {
struct southbridge_intel_i82371eb_config *sb = dev->chip_info; struct southbridge_intel_i82371eb_config *sb = dev->chip_info;
@ -92,12 +87,6 @@ static void pwrmgt_enable(struct device *dev)
outw(0xffff, DEFAULT_PMBASE + GLBSTS); outw(0xffff, DEFAULT_PMBASE + GLBSTS);
outl(0xffffffff, DEFAULT_PMBASE + DEVSTS); outl(0xffffffff, DEFAULT_PMBASE + DEVSTS);
#if CONFIG_HAVE_ACPI_RESUME
/* this reads PMCNTRL, so we have to call it before writing the
* default value */
acpi_slp_type = acpi_get_sleep_type();
#endif
/* set PMCNTRL default */ /* set PMCNTRL default */
outw(SUS_TYP_S0|SCI_EN, DEFAULT_PMBASE + PMCNTRL); outw(SUS_TYP_S0|SCI_EN, DEFAULT_PMBASE + PMCNTRL);
} }

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@ -19,12 +19,11 @@
*/ */
#include <stdint.h> #include <stdint.h>
#include <arch/acpi.h>
#include <arch/io.h> #include <arch/io.h>
#include <console/console.h> #include <console/console.h>
#include "i82371eb.h" #include "i82371eb.h"
int acpi_get_sleep_type(void);
/* /*
* Intel 82371EB (PIIX4E) datasheet, section 7.2.3, page 142 * Intel 82371EB (PIIX4E) datasheet, section 7.2.3, page 142
* *

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@ -180,11 +180,9 @@ static inline int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos)
return nvram_pos; return nvram_pos;
} }
#if CONFIG_HAVE_ACPI_RESUME
unsigned long get_top_of_ram(void) unsigned long get_top_of_ram(void)
{ {
if (!acpi_is_wakeup_early()) if (acpi_get_sleep_type() != 3)
return 0; return 0;
return (unsigned long) inl(K8T890_NVRAM_IO_BASE+K8T890_NVRAM_TOP_OF_RAM); return (unsigned long) inl(K8T890_NVRAM_IO_BASE+K8T890_NVRAM_TOP_OF_RAM);
} }
#endif

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@ -330,8 +330,7 @@ void enable_rom_decode(void)
pci_write_config8(dev, 0x41, 0x7f); pci_write_config8(dev, 0x41, 0x7f);
} }
#if CONFIG_HAVE_ACPI_RESUME int acpi_get_sleep_type(void)
int acpi_is_wakeup_early(void)
{ {
device_t dev; device_t dev;
u16 tmp; u16 tmp;
@ -354,7 +353,6 @@ int acpi_is_wakeup_early(void)
printk(BIOS_DEBUG, "%02x", tmp); printk(BIOS_DEBUG, "%02x", tmp);
return ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0 ; return ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0 ;
} }
#endif
#if defined(__GNUC__) #if defined(__GNUC__)
void vt8237_early_spi_init(void) void vt8237_early_spi_init(void)

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@ -244,10 +244,6 @@ static void setup_pm(device_t dev)
/* SCI is generated for RTC/pwrBtn/slpBtn. */ /* SCI is generated for RTC/pwrBtn/slpBtn. */
tmp = inw(VT8237R_ACPI_IO_BASE + 0x04); tmp = inw(VT8237R_ACPI_IO_BASE + 0x04);
#if CONFIG_HAVE_ACPI_RESUME
acpi_slp_type = ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0 ;
printk(BIOS_DEBUG, "SLP_TYP type was %x %x\n", tmp, acpi_slp_type);
#endif
/* All SMI on, both IDE buses ON, PSON rising edge. */ /* All SMI on, both IDE buses ON, PSON rising edge. */
outw(0x1, VT8237R_ACPI_IO_BASE + 0x2c); outw(0x1, VT8237R_ACPI_IO_BASE + 0x2c);
@ -258,6 +254,12 @@ static void setup_pm(device_t dev)
outw(tmp, VT8237R_ACPI_IO_BASE + 0x04); outw(tmp, VT8237R_ACPI_IO_BASE + 0x04);
} }
int acpi_get_sleep_type(void)
{
u16 tmp = inw(VT8237R_ACPI_IO_BASE + 0x04);
return ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0 ;
}
static void vt8237r_init(struct device *dev) static void vt8237r_init(struct device *dev)
{ {
u8 enables; u8 enables;