diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index 2f8f3da429..9fe2668899 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -11,6 +11,12 @@ config SOC_INTEL_ALDERLAKE_PCH_M
 	help
 	  Choose this option if your mainboard has a PCH-M chipset.
 
+config SOC_INTEL_ALDERLAKE_PCH_N
+	bool
+	select SOC_INTEL_ALDERLAKE
+	help
+	  Choose this option if your mainboard has a PCH-N chipset.
+
 config SOC_INTEL_ALDERLAKE_PCH_P
 	bool
 	select SOC_INTEL_ALDERLAKE
@@ -178,11 +184,13 @@ endif # SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
 config MAX_PCH_ROOT_PORTS
 	int
 	default 10 if SOC_INTEL_ALDERLAKE_PCH_M
+	default 12 if SOC_INTEL_ALDERLAKE_PCH_N
 	default 12 if SOC_INTEL_ALDERLAKE_PCH_P
 
 config MAX_CPU_ROOT_PORTS
 	int
 	default 1 if SOC_INTEL_ALDERLAKE_PCH_M
+	default 0 if SOC_INTEL_ALDERLAKE_PCH_N
 	default 3 if SOC_INTEL_ALDERLAKE_PCH_P
 
 config MAX_ROOT_PORTS
@@ -192,11 +200,13 @@ config MAX_ROOT_PORTS
 config MAX_PCIE_CLOCK_SRC
 	int
 	default 6 if SOC_INTEL_ALDERLAKE_PCH_M
+	default 5 if SOC_INTEL_ALDERLAKE_PCH_N
 	default 7 if SOC_INTEL_ALDERLAKE_PCH_P
 
 config MAX_PCIE_CLOCK_REQ
 	int
 	default 6  if SOC_INTEL_ALDERLAKE_PCH_M
+	default 5  if SOC_INTEL_ALDERLAKE_PCH_N
 	default 10 if SOC_INTEL_ALDERLAKE_PCH_P
 
 config SMM_TSEG_SIZE
diff --git a/src/soc/intel/alderlake/include/soc/bootblock.h b/src/soc/intel/alderlake/include/soc/bootblock.h
index 059568d09b..ce2e42e6b2 100644
--- a/src/soc/intel/alderlake/include/soc/bootblock.h
+++ b/src/soc/intel/alderlake/include/soc/bootblock.h
@@ -4,6 +4,7 @@
 #define _SOC_ALDERLAKE_BOOTBLOCK_H_
 
 #if	CONFIG(SOC_INTEL_ALDERLAKE_PCH_M) +	\
+	CONFIG(SOC_INTEL_ALDERLAKE_PCH_N) +	\
 	CONFIG(SOC_INTEL_ALDERLAKE_PCH_P) != 1
 #error "Please select exactly one PCH type"
 #endif