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Revert "mb/google/brya: Enable asynchronous End-Of-Post" 

This reverts commit 11f2f88a27.

Revert initial change as it was causing a boot failure when
transitioning into recovery mode.

BUG=b:276927816
TEST='emerge-brya coreboot chromeos-bootimage', flash and boot a skolas
SKU1 to kernel, then press Esc-Refresh-PowerButton to try to reboot into
recovery mode.

Change-Id: I91c8d0434a2354dedfa49dd6100caf0e5bfe3f4c
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74206
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eran Mitrani <mitrani@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Nick Vaccaro 2023-04-04 11:40:00 -07:00 committed by Subrata Banik
parent 2439b2e8ba
commit 78d0e807a9
2 changed files with 1 additions and 2 deletions
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1
src/mainboard/google/brya/Kconfig
View File

@ -32,7 +32,6 @@ config BOARD_GOOGLE_BRYA_COMMON
select PMC_IPC_ACPI_INTERFACE select PMC_IPC_ACPI_INTERFACE
select SOC_INTEL_COMMON_BLOCK_PCIE_RTD3 select SOC_INTEL_COMMON_BLOCK_PCIE_RTD3
select SOC_INTEL_CSE_LITE_SKU select SOC_INTEL_CSE_LITE_SKU
select SOC_INTEL_CSE_SEND_EOP_ASYNC
select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES if SOC_INTEL_ALDERLAKE_PCH_P select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES if SOC_INTEL_ALDERLAKE_PCH_P
select SOC_INTEL_COMMON_BASECODE_DEBUG_FEATURE select SOC_INTEL_COMMON_BASECODE_DEBUG_FEATURE
select SOC_INTEL_CRASHLOG select SOC_INTEL_CRASHLOG

2
src/soc/intel/alderlake/Kconfig
View File

@ -122,7 +122,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_FSP_RESET select SOC_INTEL_COMMON_FSP_RESET
select SOC_INTEL_COMMON_PCH_CLIENT select SOC_INTEL_COMMON_PCH_CLIENT
select SOC_INTEL_COMMON_RESET select SOC_INTEL_COMMON_RESET
select SOC_INTEL_CSE_SEND_EOP_LATE if !BOARD_GOOGLE_BRYA_COMMON select SOC_INTEL_CSE_SEND_EOP_LATE
select SOC_INTEL_CSE_SET_EOP select SOC_INTEL_CSE_SET_EOP
select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION
select HAVE_INTEL_COMPLIANCE_TEST_MODE select HAVE_INTEL_COMPLIANCE_TEST_MODE