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mb/google/drallion: Set UART for console to UART controller 0 

Drallion uses UART 0 for console, change the config accordindly.

BUG=b:139095062

Change-Id: I0ae2f8459b6225b99b758180413afa22386355d4
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35633
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Aamir Bohra 2019-09-27 07:13:46 +05:30 committed by Patrick Georgi
parent 965881b7ce
commit 78d6ce45d4
2 changed files with 3 additions and 3 deletions
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2
src/mainboard/google/drallion/Kconfig
View File

@ -91,7 +91,7 @@ config MAX_CPUS
config UART_FOR_CONSOLE config UART_FOR_CONSOLE
int int
default 2 default 0
config VARIANT_DIR config VARIANT_DIR
string string

4
src/mainboard/google/drallion/variants/drallion/devicetree.cb
View File

@ -389,7 +389,7 @@ chip soc/intel/cannonlake
end end
end # I2C #4 end # I2C #4
device pci 19.1 off end # I2C #5 device pci 19.1 off end # I2C #5
device pci 19.2 on end # UART #2 device pci 19.2 off end # UART #2
device pci 1a.0 off end # eMMC device pci 1a.0 off end # eMMC
device pci 1c.0 off end # PCI Express Port 1 (USB) device pci 1c.0 off end # PCI Express Port 1 (USB)
device pci 1c.1 off end # PCI Express Port 2 (USB) device pci 1c.1 off end # PCI Express Port 2 (USB)
@ -408,7 +408,7 @@ chip soc/intel/cannonlake
device pci 1d.4 on device pci 1d.4 on
smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "2280" "SlotDataBusWidth4X" smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "2280" "SlotDataBusWidth4X"
end # PCI Express Port 13 (x4) end # PCI Express Port 13 (x4)
device pci 1e.0 off end # UART #0 device pci 1e.0 on end # UART #0
device pci 1e.1 off end # UART #1 device pci 1e.1 off end # UART #1
device pci 1e.2 off end # GSPI #0 device pci 1e.2 off end # GSPI #0
device pci 1e.3 off end # GSPI #1 device pci 1e.3 off end # GSPI #1