Updated ep405pc to latest config system.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1984 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Greg Watson
parent
304f24c2d2
commit
78e0b0edf4
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@ -64,20 +64,20 @@ makerule linuxbios_ram.rom
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action "cp $(LINUXBIOS_RAM-1) linuxbios_ram.rom"
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end
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if CONFIG_USE_INIT
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makerule init.o
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depends "$(INIT-OBJECTS)"
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action "$(LD) -melf_i386 -r -o init.pre.o $(INIT-OBJECTS)"
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action "$(OBJCOPY) --rename-section .text=.init.text --rename-section .data=.init.data --rename-section .rodata=.init.rodata --rename-section .rodata.str1.1=.init.rodata.str1.1 init.pre.o init.o"
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end
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makerule linuxbios
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depends "crt0.o init.o linuxbios_ram.rom ldscript.ld"
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action "$(CC) -nostdlib -nostartfiles -static -o $@ -T ldscript.ld crt0.o init.o"
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action "$(CROSS_COMPILE)nm -n linuxbios | sort > linuxbios.map"
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end
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else
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#if CONFIG_USE_INIT
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#makerule init.o
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#depends "$(INIT-OBJECTS)"
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#action "$(LD) -melf_i386 -r -o init.pre.o $(INIT-OBJECTS)"
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#action "$(OBJCOPY) --rename-section .text=.init.text --rename-section .data=.init.data --rename-section .rodata=.init.rodata --rename-section .rodata.str1.1=.init.rodata.str1.1 init.pre.o init.o"
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#end
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#
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#makerule linuxbios
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# depends "crt0.o init.o linuxbios_ram.rom ldscript.ld"
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# action "$(CC) -nostdlib -nostartfiles -static -o $@ -T ldscript.ld crt0.o init.o"
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# action "$(CROSS_COMPILE)nm -n linuxbios | sort > linuxbios.map"
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#end
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#
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#else
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makerule linuxbios
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depends "crt0.o $(INIT-OBJECTS) linuxbios_ram.rom ldscript.ld"
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@ -85,7 +85,7 @@ makerule linuxbios
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action "$(CROSS_COMPILE)nm -n linuxbios | sort > linuxbios.map"
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end
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end
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#end
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makerule linuxbios.a
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depends "$(OBJECTS)"
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@ -20,8 +20,10 @@ initobject cache.S
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initobject sdram.c
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initobject clock.c
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object mem.o
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config chip.h
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object clock.o
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object cache.S
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object pci_domain.o
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driver pci_bridge.o
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dir /cpu/simple_init
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@ -0,0 +1,4 @@
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struct cpu_ppc_ppc4xx_config
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{
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};
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extern struct chip_operations cpu_ppc_ppc4xx_ops;
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4
src/mainboard/embeddedplanet/ep405pc/pci_bridge.c → src/cpu/ppc/ppc4xx/pci_bridge.c
Normal file → Executable file
4
src/mainboard/embeddedplanet/ep405pc/pci_bridge.c → src/cpu/ppc/ppc4xx/pci_bridge.c
Normal file → Executable file
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@ -8,7 +8,7 @@
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#include <console/console.h>
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static void
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pci_bridge_init(struct device *dev)
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pci_bridge_enable(struct device *dev)
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{
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printk_info("Configure PCI Bridge\n");
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@ -22,7 +22,7 @@ struct device_operations pci_bridge_ops = {
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.read_resources = pci_dev_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_dev_enable_resources,
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.init = pci_bridge_init,
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.enable = pci_bridge_enable,
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.scan_bus = 0,
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};
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@ -0,0 +1,74 @@
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/*
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* Initialisation of the PCI bridge .
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*/
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#include <arch/io.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <console/console.h>
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static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
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{
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max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
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return max;
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}
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static void pci_domain_read_resources(device_t dev)
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{
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struct resource *resource;
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/* Initialize the system wide io space constraints */
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resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0));
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resource->limit = 0xffffUL;
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resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
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/* Initialize the system wide memory resources constraints */
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resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0));
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resource->limit = 0xffffffffULL;
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resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
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}
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static void ram_resource(device_t dev, unsigned long index,
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unsigned long basek, unsigned long sizek)
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{
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struct resource *resource;
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if (!sizek) {
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return;
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}
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resource = new_resource(dev, index);
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resource->base = ((resource_t)basek) << 10;
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resource->size = ((resource_t)sizek) << 10;
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resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
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IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
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}
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static void pci_domain_set_resources(device_t dev)
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{
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int idx = 3; /* who knows? */
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ram_resource(dev, idx, 0, EMBEDDED_RAM_SIZE>>10);
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assign_resources(&dev->link[0]);
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}
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struct device_operations pci_domain_ops = {
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.read_resources = pci_domain_read_resources,
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.set_resources = pci_domain_set_resources,
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.enable_resources = enable_childrens_resources,
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.init = 0,
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.scan_bus = pci_domain_scan_bus,
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.ops_pci_bus = &pci_ppc_conf1
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};
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static void enable_dev(struct device *dev)
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{
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/* Set the operations if it is a special bus type */
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if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
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dev->ops = &pci_domain_ops;
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}
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}
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struct chip_operations cpu_ppc_ppc4xx_ops = {
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CHIP_NAME("PPC 4XX CPU")
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.enable_dev = enable_dev,
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};
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@ -17,7 +17,7 @@ makedefine .PHONY : version.o
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if CONFIG_USE_INIT
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initobject uart8250.c
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# initobject memset.o
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initobject memset.o
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initobject memcpy.o
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# initobject memcmp.o
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initobject memcmp.o
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end
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@ -6,16 +6,19 @@
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## Early board initialization, called from ppc_main()
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##
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initobject init.c
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driver pci_bridge.c
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arch ppc end
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chip cpu/ppc/ppc4xx device pnp 0.0 on end end
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##
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## Include the secondary Configuration files
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##
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chip southbridge/winbond/w83c553 device pnp 0.0 on end end
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chip cpu/ppc/ppc4xx
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device pci_domain 0 on
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device pci 0.0 on end
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chip southbridge/winbond/w83c553
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device pci 9.0 on end # ISA bridge
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device pci 9.1 on end # IDE contoller
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end
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device pci e.0 on end
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end
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end
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##
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## Build the objects we have code for in this directory.
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##
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@ -69,8 +69,8 @@ default _IO_BASE=ISA_IO_BASE
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default TTYS0_BASE=0xef600300-ISA_IO_BASE
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## Enable PPC405 instructions
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default CPU_OPT="-Wa,-m405"
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default CPU_OPT=""
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default CPU_OPT="-mcpu=405"
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#default CPU_OPT=""
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## Use stage 1 initialization code
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default CONFIG_USE_INIT=1
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@ -1,96 +1,66 @@
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# Config file for Embedded Planet EP405PC board
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# This will make a target directory of ./ep405pc
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loadoptions
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target ep405pc
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uses CPU_OPT
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uses CROSS_COMPILE
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uses HAVE_OPTION_TABLE
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uses CONFIG_COMPRESS
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uses CONFIG_CHIP_CONFIGURE
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uses DEFAULT_CONSOLE_LOGLEVEL
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uses CONFIG_USE_INIT
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uses CONFIG_CONSOLE_SERIAL8250
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uses TTYS0_BAUD TTYS0_DIV
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uses NO_POST
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uses CONFIG_IDE
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uses CONFIG_FS_STREAM
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uses CONFIG_FS_EXT2
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uses CONFIG_FS_ISO9660
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uses CONFIG_FS_FAT
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uses AUTOBOOT_CMDLINE
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uses CONFIG_SYS_CLK_FREQ
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uses IDE_BOOT_DRIVE
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uses IDE_SWAB IDE_OFFSET
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uses ROM_SIZE
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uses _RESET
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uses _EXCEPTION_VECTORS
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uses _ROMBASE
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uses _ROMSTART
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uses _RAMBASE
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uses _RAMSTART
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uses EMBEDDED_RAM_SIZE
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uses STACK_SIZE HEAP_SIZE
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## Enable PPC405 instructions
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option CPU_OPT="-Wa,-m405"
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## use a cross compiler
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#option CROSS_COMPILE="powerpc-eabi-"
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## Use stage 1 initialization code
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option CONFIG_USE_INIT=1
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## Use chip configuration
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option CONFIG_CHIP_CONFIGURE=1
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## We don't use compressed image
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option CONFIG_COMPRESS=0
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## Turn off POST codes
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option NO_POST=1
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## Enable serial console
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option DEFAULT_CONSOLE_LOGLEVEL=8
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option CONFIG_CONSOLE_SERIAL8250=1
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# Divisor of 69 == 9600 baud due to weird clocking
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option TTYS0_DIV=69
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option TTYS0_BAUD=9600
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## Boot linux from IDE
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option CONFIG_IDE=1
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option CONFIG_FS_STREAM=1
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option CONFIG_FS_EXT2=1
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option CONFIG_FS_ISO9660=1
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option CONFIG_FS_FAT=1
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option AUTOBOOT_CMDLINE="hda1:/vmlinuz"
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option ROM_SIZE=1048576
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## Board has fixed size RAM
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option EMBEDDED_RAM_SIZE=64*1024*1024
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## LinuxBIOS C code runs at this location in RAM
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option _RAMBASE=0x00100000
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##
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## Use a 64K stack
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##
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option STACK_SIZE=0x10000
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##
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## Use a 64K heap
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##
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option HEAP_SIZE=0x10000
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##
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## System clock
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##
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option CONFIG_SYS_CLK_FREQ=33
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mainboard embeddedplanet/ep405pc
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romimage "normal"
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## Enable PPC405 instructions
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option CPU_OPT="-mcpu=405"
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## use a cross compiler
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#option CROSS_COMPILE="powerpc-ibm-eabi-"
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## Use stage 1 initialization code
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option CONFIG_USE_INIT=1
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## Use chip configuration
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option CONFIG_CHIP_CONFIGURE=1
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## We don't use compressed image
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option CONFIG_COMPRESS=0
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## Turn off POST codes
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option NO_POST=1
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## Enable serial console
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option DEFAULT_CONSOLE_LOGLEVEL=8
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option CONFIG_CONSOLE_SERIAL8250=1
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# Divisor of 69 == 9600 baud due to weird clocking
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option TTYS0_DIV=69
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option TTYS0_BAUD=9600
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## Boot linux from IDE
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option CONFIG_IDE=1
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option CONFIG_FS_STREAM=1
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option CONFIG_FS_EXT2=1
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option CONFIG_FS_ISO9660=1
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option CONFIG_FS_FAT=1
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option AUTOBOOT_CMDLINE="hda1:/vmlinuz"
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option ROM_SIZE=1048576
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## Board has fixed size RAM
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option EMBEDDED_RAM_SIZE=64*1024*1024
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## LinuxBIOS C code runs at this location in RAM
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option _RAMBASE=0x00100000
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##
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## Use a 64K stack
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##
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option STACK_SIZE=0x10000
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##
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## Use a 64K heap
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##
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option HEAP_SIZE=0x10000
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##
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## System clock
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##
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option CONFIG_SYS_CLK_FREQ=33
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##
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option _ROMBASE=0xfff00000
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@ -106,7 +76,6 @@ romimage "normal"
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## linuxBIOS C code runs at this location in RAM
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option _RAMBASE=0x00100000
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mainboard embeddedplanet/ep405pc
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end
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buildrom ./linuxbios.rom ROM_SIZE "normal"
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