Updated ep405pc to latest config system.

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1984 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

src/config/Config.lb

@@ -64,20 +64,20 @@ makerule linuxbios_ram.rom
 	action	"cp $(LINUXBIOS_RAM-1) linuxbios_ram.rom"
 end
 
-if CONFIG_USE_INIT
-makerule init.o
-        depends "$(INIT-OBJECTS)"
-        action  "$(LD) -melf_i386 -r -o init.pre.o $(INIT-OBJECTS)"
-        action  "$(OBJCOPY) --rename-section .text=.init.text --rename-section .data=.init.data --rename-section .rodata=.init.rodata --rename-section .rodata.str1.1=.init.rodata.str1.1 init.pre.o init.o"
-end
-
-makerule linuxbios   
-	depends	"crt0.o init.o linuxbios_ram.rom ldscript.ld"
-	action	"$(CC) -nostdlib -nostartfiles -static -o $@ -T ldscript.ld crt0.o init.o"
-	action	"$(CROSS_COMPILE)nm -n linuxbios | sort > linuxbios.map"
-end
-
-else
+#if CONFIG_USE_INIT
+#makerule init.o
+        #depends "$(INIT-OBJECTS)"
+        #action  "$(LD) -melf_i386 -r -o init.pre.o $(INIT-OBJECTS)"
+        #action  "$(OBJCOPY) --rename-section .text=.init.text --rename-section .data=.init.data --rename-section .rodata=.init.rodata --rename-section .rodata.str1.1=.init.rodata.str1.1 init.pre.o init.o"
+#end
+#
+#makerule linuxbios   
+#	depends	"crt0.o init.o linuxbios_ram.rom ldscript.ld"
+#	action	"$(CC) -nostdlib -nostartfiles -static -o $@ -T ldscript.ld crt0.o init.o"
+#	action	"$(CROSS_COMPILE)nm -n linuxbios | sort > linuxbios.map"
+#end
+#
+#else
 
 makerule linuxbios   
 	depends	"crt0.o $(INIT-OBJECTS) linuxbios_ram.rom ldscript.ld"
@@ -85,7 +85,7 @@ makerule linuxbios
 	action	"$(CROSS_COMPILE)nm -n linuxbios | sort > linuxbios.map"
 end
 
-end
+#end
 
 makerule linuxbios.a   
 	depends	"$(OBJECTS)" 

src/cpu/ppc/ppc4xx/Config.lb

@@ -20,8 +20,10 @@ initobject cache.S
 initobject sdram.c
 initobject clock.c
 
-object mem.o
+config chip.h
 object clock.o
 object cache.S
+object pci_domain.o
+driver pci_bridge.o
 
 dir /cpu/simple_init

src/cpu/ppc/ppc4xx/chip.h

@@ -0,0 +1,4 @@
+struct cpu_ppc_ppc4xx_config
+{
+};
+extern struct chip_operations cpu_ppc_ppc4xx_ops;

src/cpu/ppc/ppc4xx/pci_bridge.c

@@ -8,7 +8,7 @@
 #include <console/console.h>
 
 static void 
-pci_bridge_init(struct device *dev)
+pci_bridge_enable(struct device *dev)
 {
 	printk_info("Configure PCI Bridge\n");
 
@@ -22,7 +22,7 @@ struct device_operations pci_bridge_ops  = {
         .read_resources   = pci_dev_read_resources,
         .set_resources    = pci_dev_set_resources,
         .enable_resources = pci_dev_enable_resources,
-        .init             = pci_bridge_init,
+        .enable           = pci_bridge_enable,
         .scan_bus         = 0,
 };
 

src/cpu/ppc/ppc4xx/pci_domain.c

@@ -0,0 +1,74 @@
+/*
+ * Initialisation of the PCI bridge .
+ */
+
+#include <arch/io.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <console/console.h>
+
+static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
+{
+	max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
+	return max;
+}
+
+static void pci_domain_read_resources(device_t dev)
+{
+	struct resource *resource;
+
+	/* Initialize the system wide io space constraints */
+	resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0));
+	resource->limit = 0xffffUL;
+	resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
+
+	/* Initialize the system wide memory resources constraints */
+	resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0));
+	resource->limit = 0xffffffffULL;
+	resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
+}
+
+static void ram_resource(device_t dev, unsigned long index,
+        unsigned long basek, unsigned long sizek)
+{
+	struct resource *resource;
+
+	if (!sizek) {
+		return;
+	}
+	resource = new_resource(dev, index);
+	resource->base  = ((resource_t)basek) << 10;
+	resource->size  = ((resource_t)sizek) << 10;
+	resource->flags =  IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
+		IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
+}
+
+static void pci_domain_set_resources(device_t dev)
+{
+	int idx = 3; /* who knows? */
+
+	ram_resource(dev, idx, 0, EMBEDDED_RAM_SIZE>>10);
+	assign_resources(&dev->link[0]);
+}
+
+struct device_operations pci_domain_ops  = {
+        .read_resources   = pci_domain_read_resources,
+        .set_resources    = pci_domain_set_resources,
+        .enable_resources = enable_childrens_resources,
+        .init             = 0,
+        .scan_bus         = pci_domain_scan_bus,
+	.ops_pci_bus	  = &pci_ppc_conf1
+};
+
+static void enable_dev(struct device *dev)
+{
+        /* Set the operations if it is a special bus type */
+        if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
+                dev->ops = &pci_domain_ops;
+        }
+}
+
+struct chip_operations cpu_ppc_ppc4xx_ops = {
+        CHIP_NAME("PPC 4XX CPU")
+        .enable_dev = enable_dev,
+};

src/lib/Config.lb

@@ -17,7 +17,7 @@ makedefine .PHONY : version.o
 
 if CONFIG_USE_INIT
 	initobject uart8250.c
-#	initobject memset.o
+	initobject memset.o
 	initobject memcpy.o
-#	initobject memcmp.o
+	initobject memcmp.o
 end

src/mainboard/embeddedplanet/ep405pc/Config.lb

@@ -6,15 +6,18 @@
 ## Early board initialization, called from ppc_main()
 ##
 initobject init.c
-driver pci_bridge.c
 
 arch ppc end
-chip cpu/ppc/ppc4xx device pnp 0.0 on end end
-
-##
-## Include the secondary Configuration files 
-##
-chip southbridge/winbond/w83c553 device pnp 0.0 on end end
+chip cpu/ppc/ppc4xx 
+	device pci_domain 0 on
+		device pci 0.0 on end
+		chip southbridge/winbond/w83c553 
+			device pci 9.0 on end # ISA bridge
+			device pci 9.1 on end # IDE contoller
+		end
+		device pci e.0 on end
+	end
+end
 	
 ##
 ## Build the objects we have code for in this directory.

src/mainboard/embeddedplanet/ep405pc/Options.lb

@@ -69,8 +69,8 @@ default _IO_BASE=ISA_IO_BASE
 default TTYS0_BASE=0xef600300-ISA_IO_BASE
 
 ## Enable PPC405 instructions
-default CPU_OPT="-Wa,-m405"
-default CPU_OPT=""
+default CPU_OPT="-mcpu=405"
+#default CPU_OPT=""
 
 ## Use stage 1 initialization code
 default CONFIG_USE_INIT=1

targets/embeddedplanet/ep405pc/Config.lb

@@ -1,44 +1,15 @@
 # Config file for Embedded Planet EP405PC board
 # This will make a target directory of ./ep405pc
 
-loadoptions
-
 target ep405pc
+mainboard embeddedplanet/ep405pc
 
-uses CPU_OPT
-uses CROSS_COMPILE 
-uses HAVE_OPTION_TABLE
-uses CONFIG_COMPRESS 
-uses CONFIG_CHIP_CONFIGURE
-uses DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_USE_INIT
-uses CONFIG_CONSOLE_SERIAL8250 
-uses TTYS0_BAUD TTYS0_DIV
-uses NO_POST
-uses CONFIG_IDE
-uses CONFIG_FS_STREAM
-uses CONFIG_FS_EXT2
-uses CONFIG_FS_ISO9660
-uses CONFIG_FS_FAT
-uses AUTOBOOT_CMDLINE
-uses CONFIG_SYS_CLK_FREQ
-uses IDE_BOOT_DRIVE
-uses IDE_SWAB IDE_OFFSET 
-uses ROM_SIZE
-uses _RESET
-uses _EXCEPTION_VECTORS
-uses _ROMBASE
-uses _ROMSTART
-uses _RAMBASE
-uses _RAMSTART
-uses EMBEDDED_RAM_SIZE
-uses STACK_SIZE HEAP_SIZE
-
+romimage "normal"
         ## Enable PPC405 instructions
-option CPU_OPT="-Wa,-m405"
+        option CPU_OPT="-mcpu=405"
 
         ## use a cross compiler
-#option CROSS_COMPILE="powerpc-eabi-"
+        #option CROSS_COMPILE="powerpc-ibm-eabi-"
 
         ## Use stage 1 initialization code
         option CONFIG_USE_INIT=1
@@ -90,7 +61,6 @@ option HEAP_SIZE=0x10000
         ##
         option CONFIG_SYS_CLK_FREQ=33
 
-romimage "normal"
 	##
 	option _ROMBASE=0xfff00000
 
@@ -106,7 +76,6 @@ romimage "normal"
 	## linuxBIOS C code runs at this location in RAM
 	option _RAMBASE=0x00100000
 
-	mainboard embeddedplanet/ep405pc
 end
 
 buildrom ./linuxbios.rom ROM_SIZE "normal"