soc/amd/cezanne/acpi: Add support for RTC workaround

The RTC on Cezanne is an unstable wake source when the system is in
S0i3. We instead need to use an internal timer that triggers a GPIO that
acts as a wake source. This change provides the ACPI necessary to allow
the OS to manage the wake source.

BUG=b:209705576
TEST=Boot guybrush with this patch and several OS patches. Verified the
OS sets the correct wake bit, the system correctly suspends
and resumes, and the wake source is correctly accounted for.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I1f14d14df5d30d48d244416f2ec8c10ac5c8040e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60172
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Limonciello <mario.limonciello@amd.corp-partner.google.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>

src/soc/amd/cezanne/acpi/rtc_workaround.asl

@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/*
+ * Workaround for RTC on Cezanne.
+ * See https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/third_party/kernel/v5.10/drivers/platform/x86/amd-pmc.c;l=416;drc=54a96af06ae6851e4a02e8dd700de0d579ef7839
+ */
+
+Scope (\_SB.PEP) {
+	Name (_PRW, Package () {
+		Package() {\_SB.GPIO, 0},
+		0x03
+	})
+}
+
+Scope (\_SB.GPIO) {
+	Name (_AEI, ResourceTemplate () {
+		GpioInt(Edge, ActiveHigh, ExclusiveAndWake, PullNone, 0x0000, "\\_SB.GPIO",,,,)
+		{
+			44 /* int_shdwsysalarmfire */
+		}
+	})
+
+	Method (_E2C, 0, Serialized) {
+		Notify (\_SB_.PEP, 0x02)
+	}
+}

src/soc/amd/cezanne/acpi/soc.asl

@@ -27,6 +27,8 @@ Scope(\_SB) {
 
 #include <soc/amd/common/acpi/upep.asl>
 
+#include "rtc_workaround.asl"
+
 /*
  * Platform Wake Notify
  *