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drivers/pc80/rtc/mc146818rtc.c: Add Kconfig for RTC CMOS base addresses 

Configure the CMOS bank I/O base addresses with
PC_CMOS_BASE_PORT_BANK* rather than hard-coding as 0x70, 0x72.  The
defaults remain the same.

Change-Id: Ie44e5f5191c66f44e2df8ea0ff58a860be88bfcf
Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74903
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Jonathon Hall 2023-05-01 13:42:46 -04:00 committed by Matt DeVillier
parent e12b313844
commit 78f8343c70
3 changed files with 23 additions and 14 deletions
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8
src/drivers/pc80/rtc/Kconfig
View File

@ -9,3 +9,11 @@ config USE_PC_CMOS_ALTCENTURY
depends on DRIVERS_MC146818
help
May be useful for legacy OSes that assume its presence.
config PC_CMOS_BASE_PORT_BANK0
hex "Base port for CMOS bank 0 index/data registers"
default 0x70
config PC_CMOS_BASE_PORT_BANK1
hex "Base port for CMOS bank 1 index/data registers"
default 0x72

8
src/drivers/pc80/rtc/mc146818rtc.c
View File

@ -249,11 +249,11 @@ void set_boot_successful(void)
{
uint8_t index, byte;
index = inb(RTC_PORT(0)) & 0x80;
index = inb(RTC_PORT_BANK0(0)) & 0x80;
index |= RTC_BOOT_BYTE;
outb(index, RTC_PORT(0));
outb(index, RTC_PORT_BANK0(0));
byte = inb(RTC_PORT(1));
byte = inb(RTC_PORT_BANK0(1));
if (CONFIG(SKIP_MAX_REBOOT_CNT_CLEAR)) {
/*
@ -269,5 +269,5 @@ void set_boot_successful(void)
byte &= 0x0f;
}
outb(byte, RTC_PORT(1));
outb(byte, RTC_PORT_BANK0(1));
}

21
src/include/pc80/mc146818rtc.h
View File

@ -6,9 +6,10 @@
#include <arch/io.h>
#include <types.h>
#define RTC_BASE_PORT 0x70
#define RTC_BASE_PORT_BANK0 (CONFIG_PC_CMOS_BASE_PORT_BANK0)
#define RTC_BASE_PORT_BANK1 (CONFIG_PC_CMOS_BASE_PORT_BANK1)
#define RTC_PORT(x) (RTC_BASE_PORT + (x))
#define RTC_PORT_BANK0(x) (RTC_BASE_PORT_BANK0 + (x))
/* control registers - Moto names
*/
@ -107,24 +108,24 @@
static inline unsigned char cmos_read(unsigned char addr)
{
int offs = 0;
int port = RTC_BASE_PORT_BANK0;
if (addr >= 128) {
offs = 2;
port = RTC_BASE_PORT_BANK1;
addr -= 128;
}
outb(addr, RTC_BASE_PORT + offs + 0);
return inb(RTC_BASE_PORT + offs + 1);
outb(addr, port + 0);
return inb(port + 1);
}
static inline void cmos_write_inner(unsigned char val, unsigned char addr)
{
int offs = 0;
int port = RTC_BASE_PORT_BANK0;
if (addr >= 128) {
offs = 2;
port = RTC_BASE_PORT_BANK1;
addr -= 128;
}
outb(addr, RTC_BASE_PORT + offs + 0);
outb(val, RTC_BASE_PORT + offs + 1);
outb(addr, port + 0);
outb(val, port + 1);
}
static inline u8 cmos_disable_rtc(void)