soc/intel/cannonlake: Add null reference check for Cnvi and Xdci
Change-Id: I2e1011d9ac93ed764b6c2aa425928a972ec2aa43 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32322 Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
parent
5f28639a93
commit
78fbe3d831
|
@ -245,9 +245,12 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
|
||||||
|
|
||||||
/* Enable xDCI controller if enabled in devicetree and allowed */
|
/* Enable xDCI controller if enabled in devicetree and allowed */
|
||||||
dev = dev_find_slot(0, PCH_DEVFN_USBOTG);
|
dev = dev_find_slot(0, PCH_DEVFN_USBOTG);
|
||||||
if (!xdci_can_enable())
|
if (dev) {
|
||||||
dev->enabled = 0;
|
if (!xdci_can_enable())
|
||||||
params->XdciEnable = dev->enabled;
|
dev->enabled = 0;
|
||||||
|
params->XdciEnable = dev->enabled;
|
||||||
|
} else
|
||||||
|
params->XdciEnable = 0;
|
||||||
|
|
||||||
/* Set Debug serial port */
|
/* Set Debug serial port */
|
||||||
params->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE;
|
params->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE;
|
||||||
|
@ -255,9 +258,15 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
|
||||||
/* Enable CNVi Wifi if enabled in device tree */
|
/* Enable CNVi Wifi if enabled in device tree */
|
||||||
dev = dev_find_slot(0, PCH_DEVFN_CNViWIFI);
|
dev = dev_find_slot(0, PCH_DEVFN_CNViWIFI);
|
||||||
#if CONFIG(SOC_INTEL_COMETLAKE)
|
#if CONFIG(SOC_INTEL_COMETLAKE)
|
||||||
params->CnviMode = dev->enabled;
|
if (dev)
|
||||||
|
params->CnviMode = dev->enabled;
|
||||||
|
else
|
||||||
|
params->CnviMode = 0;
|
||||||
#else
|
#else
|
||||||
params->PchCnviMode = dev->enabled;
|
if (dev)
|
||||||
|
params->PchCnviMode = dev->enabled;
|
||||||
|
else
|
||||||
|
params->PchCnviMode = 0;
|
||||||
#endif
|
#endif
|
||||||
/* PCI Express */
|
/* PCI Express */
|
||||||
for (i = 0; i < ARRAY_SIZE(config->PcieClkSrcUsage); i++) {
|
for (i = 0; i < ARRAY_SIZE(config->PcieClkSrcUsage); i++) {
|
||||||
|
|
Loading…
Reference in New Issue