soc/intel/cannonlake: Add null reference check for Cnvi and Xdci
Change-Id: I2e1011d9ac93ed764b6c2aa425928a972ec2aa43 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32322 Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -245,9 +245,12 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
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/* Enable xDCI controller if enabled in devicetree and allowed */
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dev = dev_find_slot(0, PCH_DEVFN_USBOTG);
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if (!xdci_can_enable())
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dev->enabled = 0;
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params->XdciEnable = dev->enabled;
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if (dev) {
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if (!xdci_can_enable())
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dev->enabled = 0;
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params->XdciEnable = dev->enabled;
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} else
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params->XdciEnable = 0;
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/* Set Debug serial port */
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params->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE;
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@ -255,9 +258,15 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
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/* Enable CNVi Wifi if enabled in device tree */
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dev = dev_find_slot(0, PCH_DEVFN_CNViWIFI);
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#if CONFIG(SOC_INTEL_COMETLAKE)
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params->CnviMode = dev->enabled;
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if (dev)
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params->CnviMode = dev->enabled;
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else
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params->CnviMode = 0;
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#else
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params->PchCnviMode = dev->enabled;
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if (dev)
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params->PchCnviMode = dev->enabled;
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else
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params->PchCnviMode = 0;
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#endif
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/* PCI Express */
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for (i = 0; i < ARRAY_SIZE(config->PcieClkSrcUsage); i++) {
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