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soc/intel/cannonlake: Add options for pcie ltr 

FSP can support enable/disable Pci express LTR (Latency Tolerance
Reporting) mechanism through upd interface. Include that into coreboot
side.

BUG=N/A
TEST=N/A

Change-Id: I69b423afa4f81a2d58375734bba07792e08931d5
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/29642
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Lijian Zhao 2018-11-14 16:15:46 -08:00 committed by Patrick Georgi
parent 28114ae71b
commit 79152f3c81
2 changed files with 4 additions and 0 deletions
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2
src/soc/intel/cannonlake/chip.h
View File

@ -154,6 +154,8 @@ struct soc_intel_cannonlake_config {
/* PCIe ClkReq-to-ClkSrc mapping, number of clkreq signal assigned to /* PCIe ClkReq-to-ClkSrc mapping, number of clkreq signal assigned to
* clksrc. */ * clksrc. */
uint8_t PcieClkSrcClkReq[CONFIG_MAX_ROOT_PORTS]; uint8_t PcieClkSrcClkReq[CONFIG_MAX_ROOT_PORTS];
/* PCIe LTR(Latency Tolerance Reporting) mechanism */
uint8_t PcieRpLtrEnable[CONFIG_MAX_ROOT_PORTS];
/* eMMC and SD */ /* eMMC and SD */
uint8_t ScsEmmcHs400Enabled; uint8_t ScsEmmcHs400Enabled;

2
src/soc/intel/cannonlake/fsp_params.c
View File

@ -171,6 +171,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
sizeof(config->PcieClkSrcUsage)); sizeof(config->PcieClkSrcUsage));
memcpy(params->PcieClkSrcClkReq, config->PcieClkSrcClkReq, memcpy(params->PcieClkSrcClkReq, config->PcieClkSrcClkReq,
sizeof(config->PcieClkSrcClkReq)); sizeof(config->PcieClkSrcClkReq));
memcpy(params->PcieRpLtrEnable, config->PcieRpLtrEnable,
sizeof(config->PcieRpLtrEnable));
/* eMMC and SD */ /* eMMC and SD */
dev = dev_find_slot(0, PCH_DEVFN_EMMC); dev = dev_find_slot(0, PCH_DEVFN_EMMC);