AMD Geode cpus: apply un-written naming rules

Kconfig directives to select chip drivers for compile literally
match the chip directory names capitalized and underscored.

Rename directories and Kconfig as follows:
   model_lx  -> geode_lx
   model_gx1 -> geode_gx1
   model_gx2 -> geode_gx2

Change-Id: Ib8bf1e758b88f9efed1cf8b11c76b796388e7147
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/613
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

src/cpu/amd/Kconfig

@@ -16,9 +16,9 @@ source src/cpu/amd/socket_S1G1/Kconfig
 
 source src/cpu/amd/model_fxx/Kconfig
 source src/cpu/amd/model_10xxx/Kconfig
-source src/cpu/amd/model_gx1/Kconfig
-source src/cpu/amd/model_gx2/Kconfig
-source src/cpu/amd/model_lx/Kconfig
+source src/cpu/amd/geode_gx1/Kconfig
+source src/cpu/amd/geode_gx2/Kconfig
+source src/cpu/amd/geode_lx/Kconfig
 
 source src/cpu/amd/sc520/Kconfig
 

src/cpu/amd/Makefile.inc

@@ -8,9 +8,9 @@ subdirs-$(CONFIG_CPU_AMD_SOCKET_AM2R2) += socket_AM2r2
 subdirs-$(CONFIG_CPU_AMD_SOCKET_AM3) += socket_AM3
 subdirs-$(CONFIG_CPU_AMD_SOCKET_ASB2) += socket_ASB2
 subdirs-$(CONFIG_CPU_AMD_SOCKET_C32) += socket_C32
-subdirs-$(CONFIG_CPU_AMD_GX1) += model_gx1
-subdirs-$(CONFIG_CPU_AMD_GX2) += model_gx2
-subdirs-$(CONFIG_CPU_AMD_LX) += model_lx
+subdirs-$(CONFIG_CPU_AMD_GEODE_GX1) += geode_gx1
+subdirs-$(CONFIG_CPU_AMD_GEODE_GX2) += geode_gx2
+subdirs-$(CONFIG_CPU_AMD_GEODE_LX) += geode_lx
 subdirs-$(CONFIG_CPU_AMD_SC520) += sc520
 subdirs-$(CONFIG_CPU_AMD_SOCKET_S1G1) += socket_S1G1
 

src/cpu/amd/geode_gx1/Kconfig

@@ -17,16 +17,17 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-config CPU_AMD_GX1
+config CPU_AMD_GEODE_GX1
 	bool
 
+if CPU_AMD_GEODE_GX1
+
 config DCACHE_RAM_BASE
 	hex
 	default 0xc0000
-	depends on CPU_AMD_GX1
 
 config DCACHE_RAM_SIZE
 	hex
 	default 0x01000
-	depends on CPU_AMD_GX1
 
+endif # CPU_AMD_GEODE_GX1

src/cpu/amd/geode_gx1/Makefile.inc

@@ -22,7 +22,7 @@ subdirs-y += ../../x86/tsc
 subdirs-y += ../../x86/lapic
 subdirs-y += ../../x86/cache
 subdirs-y += ../../x86/smm
-driver-y += model_gx1_init.c
+driver-y += geode_gx1_init.c
 
-cpu_incs += $(src)/cpu/amd/model_gx1/cpu_setup.inc
-cpu_incs += $(src)/cpu/amd/model_gx1/gx_setup.inc
+cpu_incs += $(src)/cpu/amd/geode_gx1/cpu_setup.inc
+cpu_incs += $(src)/cpu/amd/geode_gx1/gx_setup.inc

src/cpu/amd/geode_gx1/geode_gx1_init.c

@@ -73,7 +73,7 @@ unsigned long addr;
 }
 #endif
 
-static void model_gx1_init(device_t dev)
+static void geode_gx1_init(device_t dev)
 {
 #if 0
 	gx1_cpu_setup();
@@ -87,7 +87,7 @@ static void model_gx1_init(device_t dev)
 };
 
 static struct device_operations cpu_dev_ops = {
-	.init	= model_gx1_init,
+	.init	= geode_gx1_init,
 };
 
 static struct cpu_device_id cpu_table[] = {

src/cpu/amd/geode_gx2/Kconfig

@@ -17,10 +17,10 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-config CPU_AMD_GX2
+config CPU_AMD_GEODE_GX2
 	bool
 
-if CPU_AMD_GX2
+if CPU_AMD_GEODE_GX2
 
 config CPU_SPECIFIC_OPTIONS
 	def_bool y
@@ -55,5 +55,4 @@ config VSA_FILENAME
 	help
 	  The path and filename of the file to use as VSA.
 
-endif # CPU_AMD_GX2
-
+endif # CPU_AMD_GEODE_GX2

src/cpu/amd/geode_gx2/Makefile.inc

@@ -3,7 +3,7 @@ subdirs-y += ../../x86/lapic
 subdirs-y += ../../x86/cache
 subdirs-y += ../../x86/smm
 
-driver-y += model_gx2_init.c
+driver-y += geode_gx2_init.c
 ramstage-y += cpubug.c
 
-cpu_incs += $(src)/cpu/amd/model_gx2/cache_as_ram.inc
+cpu_incs += $(src)/cpu/amd/geode_gx2/cache_as_ram.inc

src/cpu/amd/geode_gx2/geode_gx2_init.c

@@ -16,9 +16,9 @@ static void vsm_end_post_smi(void)
 			  );
 }
 
-static void model_gx2_init(device_t dev)
+static void geode_gx2_init(device_t dev)
 {
-	printk(BIOS_DEBUG, "model_gx2_init\n");
+	printk(BIOS_DEBUG, "geode_gx2_init\n");
 
 	/* Turn on caching if we haven't already */
 	x86_enable_cache();
@@ -28,11 +28,11 @@ static void model_gx2_init(device_t dev)
 
 	vsm_end_post_smi();
 
-	printk(BIOS_DEBUG, "model_gx2_init DONE\n");
+	printk(BIOS_DEBUG, "geode_gx2_init DONE\n");
 };
 
 static struct device_operations cpu_dev_ops = {
-	.init	= model_gx2_init,
+	.init	= geode_gx2_init,
 };
 
 static struct cpu_device_id cpu_table[] = {

src/cpu/amd/geode_lx/Kconfig

@@ -1,7 +1,7 @@
-config CPU_AMD_LX
+config CPU_AMD_GEODE_LX
 	bool
 
-if CPU_AMD_LX
+if CPU_AMD_GEODE_LX
 
 config CPU_SPECIFIC_OPTIONS
 	def_bool y
@@ -36,4 +36,4 @@ config VSA_FILENAME
 	help
 	  The path and filename of the file to use as VSA.
 
-endif # CPU_AMD_LX
+endif # CPU_AMD_GEODE_LX

src/cpu/amd/geode_lx/Makefile.inc

@@ -3,7 +3,7 @@ subdirs-y += ../../x86/lapic
 subdirs-y += ../../x86/cache
 subdirs-y += ../../x86/smm
 
-driver-y += model_lx_init.c
+driver-y += geode_lx_init.c
 ramstage-y += cpubug.c
 
-cpu_incs += $(src)/cpu/amd/model_lx/cache_as_ram.inc
+cpu_incs += $(src)/cpu/amd/geode_lx/cache_as_ram.inc

src/cpu/amd/geode_lx/geode_lx_init.c

@@ -38,9 +38,9 @@ static void vsm_end_post_smi(void)
 			  ".byte 0x0f, 0x38\n" "pop %ax\n");
 }
 
-static void model_lx_init(device_t dev)
+static void geode_lx_init(device_t dev)
 {
-	printk(BIOS_DEBUG, "model_lx_init\n");
+	printk(BIOS_DEBUG, "geode_lx_init\n");
 
 	/* Turn on caching if we haven't already */
 	x86_enable_cache();
@@ -56,11 +56,11 @@ static void model_lx_init(device_t dev)
 	outb(0x02, 0x92);
 	printk(BIOS_DEBUG, "A20 (0x92): %d\n", inb(0x92));
 
-	printk(BIOS_DEBUG, "CPU model_lx_init DONE\n");
+	printk(BIOS_DEBUG, "CPU geode_lx_init DONE\n");
 };
 
 static struct device_operations cpu_dev_ops = {
-	.init = model_lx_init,
+	.init = geode_lx_init,
 };
 
 static struct cpu_device_id cpu_table[] = {

src/include/lib.h

@@ -41,7 +41,7 @@ int ram_check_nodie(unsigned long start, unsigned long stop);
 void quick_ram_check(void);
 
 /* Defined in romstage.c */
-#if CONFIG_CPU_AMD_LX
+#if CONFIG_CPU_AMD_GEODE_LX
 void cache_as_ram_main(void);
 #else
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx);

src/mainboard/aaeon/pfm-540i_revb/Kconfig

@@ -3,7 +3,7 @@ if BOARD_AAEON_PFM_540I_REVB
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
 	select ARCH_X86
-	select CPU_AMD_LX
+	select CPU_AMD_GEODE_LX
 	select NORTHBRIDGE_AMD_LX
 	select SOUTHBRIDGE_AMD_CS5536
 	select SUPERIO_SMSC_SMSCSUPERIO

src/mainboard/aaeon/pfm-540i_revb/devicetree.cb

@@ -66,7 +66,7 @@ chip northbridge/amd/lx
 	end
 	# APIC cluster is late CPU init.
 	device lapic_cluster 0 on
-		chip cpu/amd/model_lx
+		chip cpu/amd/geode_lx
 			device lapic 0 on end
 		end
 	end

src/mainboard/aaeon/pfm-540i_revb/romstage.c

@@ -55,9 +55,9 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
 #include "northbridge/amd/lx/pll_reset.c"
 #include "northbridge/amd/lx/raminit.c"
 #include "lib/generic_sdram.c"
-#include "cpu/amd/model_lx/cpureginit.c"
-#include "cpu/amd/model_lx/syspreinit.c"
-#include "cpu/amd/model_lx/msrinit.c"
+#include "cpu/amd/geode_lx/cpureginit.c"
+#include "cpu/amd/geode_lx/syspreinit.c"
+#include "cpu/amd/geode_lx/msrinit.c"
 
 void main(unsigned long bist)
 {

src/mainboard/advantech/pcm-5820/Kconfig

@@ -21,7 +21,7 @@ if BOARD_ADVANTECH_PCM_5820
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
 	select ARCH_X86
-	select CPU_AMD_GX1
+	select CPU_AMD_GEODE_GX1
 	select NORTHBRIDGE_AMD_GX1
 	select SOUTHBRIDGE_AMD_CS5530
 	select SUPERIO_WINBOND_W83977F

src/mainboard/advantech/pcm-5820/devicetree.cb

@@ -51,6 +51,6 @@ chip northbridge/amd/gx1		# Northbridge
       register "ide1_enable" = "1"
     end
   end
-  chip cpu/amd/model_gx1		# CPU
+  chip cpu/amd/geode_gx1		# CPU
   end
 end

src/mainboard/amd/db800/Kconfig

@@ -3,7 +3,7 @@ if BOARD_AMD_DB800
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
 	select ARCH_X86
-	select CPU_AMD_LX
+	select CPU_AMD_GEODE_LX
 	select NORTHBRIDGE_AMD_LX
 	select SOUTHBRIDGE_AMD_CS5536
 	select SUPERIO_WINBOND_W83627HF

src/mainboard/amd/db800/devicetree.cb

@@ -60,7 +60,7 @@ chip northbridge/amd/lx
 	end
 	# APIC cluster is late CPU init.
 	device lapic_cluster 0 on
-		chip cpu/amd/model_lx
+		chip cpu/amd/geode_lx
 			device lapic 0 on end
 		end
 	end

src/mainboard/amd/db800/romstage.c

@@ -49,9 +49,9 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
 #include "northbridge/amd/lx/pll_reset.c"
 #include "northbridge/amd/lx/raminit.c"
 #include "lib/generic_sdram.c"
-#include "cpu/amd/model_lx/cpureginit.c"
-#include "cpu/amd/model_lx/syspreinit.c"
-#include "cpu/amd/model_lx/msrinit.c"
+#include "cpu/amd/geode_lx/cpureginit.c"
+#include "cpu/amd/geode_lx/syspreinit.c"
+#include "cpu/amd/geode_lx/msrinit.c"
 
 void main(unsigned long bist)
 {

src/mainboard/amd/norwich/Kconfig

@@ -3,7 +3,7 @@ if BOARD_AMD_NORWICH
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
 	select ARCH_X86
-	select CPU_AMD_LX
+	select CPU_AMD_GEODE_LX
 	select NORTHBRIDGE_AMD_LX
 	select SOUTHBRIDGE_AMD_CS5536
 	select HAVE_PIRQ_TABLE

src/mainboard/amd/norwich/devicetree.cb

@@ -33,7 +33,7 @@ chip northbridge/amd/lx
 	end
 	# APIC cluster is late CPU init.
 	device lapic_cluster 0 on
-		chip cpu/amd/model_lx
+		chip cpu/amd/geode_lx
 			device lapic 0 on end
 		end
 	end

src/mainboard/amd/norwich/romstage.c

@@ -46,9 +46,9 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
 #include "northbridge/amd/lx/pll_reset.c"
 #include "northbridge/amd/lx/raminit.c"
 #include "lib/generic_sdram.c"
-#include "cpu/amd/model_lx/cpureginit.c"
-#include "cpu/amd/model_lx/syspreinit.c"
-#include "cpu/amd/model_lx/msrinit.c"
+#include "cpu/amd/geode_lx/cpureginit.c"
+#include "cpu/amd/geode_lx/syspreinit.c"
+#include "cpu/amd/geode_lx/msrinit.c"
 
 void main(unsigned long bist)
 {

src/mainboard/amd/rumba/Kconfig

@@ -21,7 +21,7 @@ if BOARD_AMD_RUMBA
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
 	select ARCH_X86
-	select CPU_AMD_GX2
+	select CPU_AMD_GEODE_GX2
 	select NORTHBRIDGE_AMD_GX2
 	select SOUTHBRIDGE_AMD_CS5536
 	select UDELAY_TSC

src/mainboard/amd/rumba/devicetree.cb

@@ -1,6 +1,6 @@
 chip northbridge/amd/gx2
 	device lapic_cluster 0 on
-		chip cpu/amd/model_gx2
+		chip cpu/amd/geode_gx2
 			device lapic 0 on end
 		end
 	end

src/mainboard/amd/rumba/romstage.c

@@ -26,9 +26,9 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "northbridge/amd/gx2/pll_reset.c"
 #include "northbridge/amd/gx2/raminit.c"
 #include "lib/generic_sdram.c"
-#include "cpu/amd/model_gx2/cpureginit.c"
-#include "cpu/amd/model_gx2/syspreinit.c"
-#include "cpu/amd/model_lx/msrinit.c"
+#include "cpu/amd/geode_gx2/cpureginit.c"
+#include "cpu/amd/geode_gx2/syspreinit.c"
+#include "cpu/amd/geode_lx/msrinit.c"
 
 void main(unsigned long bist)
 {

src/mainboard/artecgroup/dbe61/Kconfig

@@ -3,7 +3,7 @@ if BOARD_ARTECGROUP_DBE61
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
 	select ARCH_X86
-	select CPU_AMD_LX
+	select CPU_AMD_GEODE_LX
 	select NORTHBRIDGE_AMD_LX
 	select SOUTHBRIDGE_AMD_CS5536
 	select HAVE_PIRQ_TABLE

src/mainboard/artecgroup/dbe61/devicetree.cb

@@ -33,7 +33,7 @@ chip northbridge/amd/lx
 	end
 	# APIC cluster is late CPU init.
 	device lapic_cluster 0 on
-		chip cpu/amd/model_lx
+		chip cpu/amd/geode_lx
 			device lapic 0 on end
 		end
 	end

src/mainboard/artecgroup/dbe61/romstage.c

@@ -61,9 +61,9 @@ static int spd_read_byte(unsigned device, unsigned address)
 #include "northbridge/amd/lx/pll_reset.c"
 #include "northbridge/amd/lx/raminit.c"
 #include "lib/generic_sdram.c"
-#include "cpu/amd/model_lx/cpureginit.c"
-#include "cpu/amd/model_lx/syspreinit.c"
-#include "cpu/amd/model_lx/msrinit.c"
+#include "cpu/amd/geode_lx/cpureginit.c"
+#include "cpu/amd/geode_lx/syspreinit.c"
+#include "cpu/amd/geode_lx/msrinit.c"
 
 void main(unsigned long bist)
 {

src/mainboard/asi/mb_5blgp/Kconfig

@@ -21,7 +21,7 @@ if BOARD_ASI_MB_5BLGP
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
 	select ARCH_X86
-	select CPU_AMD_GX1
+	select CPU_AMD_GEODE_GX1
 	select NORTHBRIDGE_AMD_GX1
 	select SOUTHBRIDGE_AMD_CS5530
 	select SUPERIO_NSC_PC87351

src/mainboard/asi/mb_5blgp/devicetree.cb

@@ -50,6 +50,6 @@ chip northbridge/amd/gx1		# Northbridge
       register "ide1_enable" = "0"	# No connector on this board
     end
   end
-  chip cpu/amd/model_gx1		# CPU
+  chip cpu/amd/geode_gx1		# CPU
   end
 end

src/mainboard/asi/mb_5blmp/Kconfig

@@ -21,7 +21,7 @@ if BOARD_ASI_MB_5BLMP
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
 	select ARCH_X86
-	select CPU_AMD_GX1
+	select CPU_AMD_GEODE_GX1
 	select NORTHBRIDGE_AMD_GX1
 	select SOUTHBRIDGE_AMD_CS5530
 	select SUPERIO_NSC_PC87351

src/mainboard/asi/mb_5blmp/devicetree.cb

@@ -42,7 +42,7 @@ chip northbridge/amd/gx1		# Northbridge
       register "ide1_enable" = "1"
     end
   end
-  chip cpu/amd/model_gx1		# CPU
+  chip cpu/amd/geode_gx1		# CPU
   end
 end
 

src/mainboard/axus/tc320/Kconfig

@@ -21,7 +21,7 @@ if BOARD_AXUS_TC320
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
 	select ARCH_X86
-	select CPU_AMD_GX1
+	select CPU_AMD_GEODE_GX1
 	select NORTHBRIDGE_AMD_GX1
 	select SOUTHBRIDGE_AMD_CS5530
 	select SUPERIO_NSC_PC97317

src/mainboard/axus/tc320/devicetree.cb

@@ -50,6 +50,6 @@ chip northbridge/amd/gx1		# Northbridge
       # register "ide1_enable" = "1"
     end
   end
-  chip cpu/amd/model_gx1		# CPU
+  chip cpu/amd/geode_gx1		# CPU
   end
 end

src/mainboard/bcom/winnet100/Kconfig

@@ -21,7 +21,7 @@ if BOARD_BCOM_WINNET100
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
 	select ARCH_X86
-	select CPU_AMD_GX1
+	select CPU_AMD_GEODE_GX1
 	select NORTHBRIDGE_AMD_GX1
 	select SOUTHBRIDGE_AMD_CS5530
 	select SUPERIO_NSC_PC97317

src/mainboard/bcom/winnet100/devicetree.cb

@@ -51,6 +51,6 @@ chip northbridge/amd/gx1		# Northbridge
       register "ide1_enable" = "0"	# Not available/needed on this board
     end
   end
-  chip cpu/amd/model_gx1		# CPU
+  chip cpu/amd/geode_gx1		# CPU
   end
 end

src/mainboard/digitallogic/msm800sev/Kconfig

@@ -3,7 +3,7 @@ if BOARD_DIGITALLOGIC_MSM800SEV
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
 	select ARCH_X86
-	select CPU_AMD_LX
+	select CPU_AMD_GEODE_LX
 	select NORTHBRIDGE_AMD_LX
 	select SOUTHBRIDGE_AMD_CS5536
 	select SUPERIO_WINBOND_W83627HF

src/mainboard/digitallogic/msm800sev/devicetree.cb

@@ -77,7 +77,7 @@ chip northbridge/amd/lx
 
 	# APIC cluster is late CPU init.
 	device lapic_cluster 0 on
-		chip cpu/amd/model_lx
+		chip cpu/amd/geode_lx
 			device lapic 0 on end
 		end
 	end

src/mainboard/digitallogic/msm800sev/romstage.c

@@ -30,9 +30,9 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "northbridge/amd/lx/pll_reset.c"
 #include "northbridge/amd/lx/raminit.c"
 #include "lib/generic_sdram.c"
-#include "cpu/amd/model_lx/cpureginit.c"
-#include "cpu/amd/model_lx/syspreinit.c"
-#include "cpu/amd/model_lx/msrinit.c"
+#include "cpu/amd/geode_lx/cpureginit.c"
+#include "cpu/amd/geode_lx/syspreinit.c"
+#include "cpu/amd/geode_lx/msrinit.c"
 
 void main(unsigned long bist)
 {

src/mainboard/eaglelion/5bcm/Kconfig

@@ -21,7 +21,7 @@ if BOARD_EAGLELION_5BCM
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
 	select ARCH_X86
-	select CPU_AMD_GX1
+	select CPU_AMD_GEODE_GX1
 	select NORTHBRIDGE_AMD_GX1
 	select SOUTHBRIDGE_AMD_CS5530
 	select SUPERIO_NSC_PC97317

src/mainboard/eaglelion/5bcm/devicetree.cb

@@ -45,7 +45,7 @@ chip northbridge/amd/gx1
     end
   end
 
-  chip cpu/amd/model_gx1
+  chip cpu/amd/geode_gx1
   end
 
 end

src/mainboard/iei/juki-511p/Kconfig

@@ -21,7 +21,7 @@ if BOARD_IEI_JUKI_511P
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
 	select ARCH_X86
-	select CPU_AMD_GX1
+	select CPU_AMD_GEODE_GX1
 	select NORTHBRIDGE_AMD_GX1
 	select SOUTHBRIDGE_AMD_CS5530
 	select SUPERIO_WINBOND_W83977F

src/mainboard/iei/juki-511p/devicetree.cb

@@ -50,7 +50,7 @@ chip northbridge/amd/gx1
     end
   end
 
-  chip cpu/amd/model_gx1
+  chip cpu/amd/geode_gx1
   end
 
 end

src/mainboard/iei/nova4899r/Kconfig

@@ -21,7 +21,7 @@ if BOARD_IEI_NOVA_4899R
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
 	select ARCH_X86
-	select CPU_AMD_GX1
+	select CPU_AMD_GEODE_GX1
 	select NORTHBRIDGE_AMD_GX1
 	select SOUTHBRIDGE_AMD_CS5530
 	select SUPERIO_WINBOND_W83977TF

src/mainboard/iei/nova4899r/devicetree.cb

@@ -57,7 +57,7 @@ chip northbridge/amd/gx1
     end
   end
 
-  chip cpu/amd/model_gx1
+  chip cpu/amd/geode_gx1
   end
 
 end

src/mainboard/iei/pcisa-lx-800-r10/Kconfig

@@ -3,7 +3,7 @@ if BOARD_IEI_PCISA_LX_800_R10
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
 	select ARCH_X86
-	select CPU_AMD_LX
+	select CPU_AMD_GEODE_LX
 	select NORTHBRIDGE_AMD_LX
 	select SOUTHBRIDGE_AMD_CS5536
 	select SUPERIO_WINBOND_W83627HF

src/mainboard/iei/pcisa-lx-800-r10/devicetree.cb

@@ -68,7 +68,7 @@ chip northbridge/amd/lx
 	end
 	# APIC cluster is late CPU init.
 	device lapic_cluster 0 on
-		chip cpu/amd/model_lx
+		chip cpu/amd/geode_lx
 			device lapic 0 on end
 		end
 	end

src/mainboard/iei/pcisa-lx-800-r10/romstage.c

@@ -53,9 +53,9 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
 #include "northbridge/amd/lx/pll_reset.c"
 #include "northbridge/amd/lx/raminit.c"
 #include "lib/generic_sdram.c"
-#include "cpu/amd/model_lx/cpureginit.c"
-#include "cpu/amd/model_lx/syspreinit.c"
-#include "cpu/amd/model_lx/msrinit.c"
+#include "cpu/amd/geode_lx/cpureginit.c"
+#include "cpu/amd/geode_lx/syspreinit.c"
+#include "cpu/amd/geode_lx/msrinit.c"
 
 void main(unsigned long bist)
 {

src/mainboard/lippert/frontrunner/Kconfig

@@ -3,7 +3,7 @@ if BOARD_LIPPERT_FRONTRUNNER
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
 	select ARCH_X86
-	select CPU_AMD_GX2
+	select CPU_AMD_GEODE_GX2
 	select NORTHBRIDGE_AMD_GX2
 	select SOUTHBRIDGE_AMD_CS5535
 	select HAVE_DEBUG_SMBUS

src/mainboard/lippert/frontrunner/devicetree.cb

@@ -1,6 +1,6 @@
 chip northbridge/amd/gx2
   device lapic_cluster 0 on
-    chip cpu/amd/model_gx2
+    chip cpu/amd/geode_gx2
       device lapic 0 on end
     end
   end

src/mainboard/lippert/frontrunner/romstage.c

@@ -66,9 +66,9 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
 #include "northbridge/amd/gx2/pll_reset.c"
 #include "northbridge/amd/gx2/raminit.c"
 #include "lib/generic_sdram.c"
-#include "cpu/amd/model_gx2/cpureginit.c"
-#include "cpu/amd/model_gx2/syspreinit.c"
-#include "cpu/amd/model_lx/msrinit.c"
+#include "cpu/amd/geode_gx2/cpureginit.c"
+#include "cpu/amd/geode_gx2/syspreinit.c"
+#include "cpu/amd/geode_lx/msrinit.c"
 
 void main(unsigned long bist)
 {

src/mainboard/lippert/hurricane-lx/Kconfig

@@ -3,7 +3,7 @@ if BOARD_LIPPERT_HURRICANE_LX
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
 	select ARCH_X86
-	select CPU_AMD_LX
+	select CPU_AMD_GEODE_LX
 	select NORTHBRIDGE_AMD_LX
 	select SOUTHBRIDGE_AMD_CS5536
 	select SUPERIO_ITE_IT8712F

src/mainboard/lippert/hurricane-lx/devicetree.cb

@@ -83,7 +83,7 @@ chip northbridge/amd/lx
   end
   # APIC cluster is late CPU init.
   device lapic_cluster 0 on
-    chip cpu/amd/model_lx
+    chip cpu/amd/geode_lx
       device lapic 0 on end
     end
   end

src/mainboard/lippert/hurricane-lx/romstage.c

@@ -77,9 +77,9 @@ static int smc_send_config(unsigned char config_data)
 #include "northbridge/amd/lx/pll_reset.c"
 #include "northbridge/amd/lx/raminit.c"
 #include "lib/generic_sdram.c"
-#include "cpu/amd/model_lx/cpureginit.c"
-#include "cpu/amd/model_lx/syspreinit.c"
-#include "cpu/amd/model_lx/msrinit.c"
+#include "cpu/amd/geode_lx/cpureginit.c"
+#include "cpu/amd/geode_lx/syspreinit.c"
+#include "cpu/amd/geode_lx/msrinit.c"
 
 static const u16 sio_init_table[] = { // hi=data, lo=index
 	0x0707,		// select LDN 7 (GPIO, SPI, watchdog, ...)

src/mainboard/lippert/literunner-lx/Kconfig

@@ -3,7 +3,7 @@ if BOARD_LIPPERT_LITERUNNER_LX
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
 	select ARCH_X86
-	select CPU_AMD_LX
+	select CPU_AMD_GEODE_LX
 	select NORTHBRIDGE_AMD_LX
 	select SOUTHBRIDGE_AMD_CS5536
 	select SUPERIO_ITE_IT8712F

src/mainboard/lippert/literunner-lx/devicetree.cb

@@ -80,7 +80,7 @@ chip northbridge/amd/lx
   end
   # APIC cluster is late CPU init.
   device lapic_cluster 0 on
-    chip cpu/amd/model_lx
+    chip cpu/amd/geode_lx
       device lapic 0 on end
     end
   end

src/mainboard/lippert/literunner-lx/romstage.c

@@ -118,9 +118,9 @@ static int smc_send_config(unsigned char config_data)
 #include "northbridge/amd/lx/pll_reset.c"
 #include "northbridge/amd/lx/raminit.c"
 #include "lib/generic_sdram.c"
-#include "cpu/amd/model_lx/cpureginit.c"
-#include "cpu/amd/model_lx/syspreinit.c"
-#include "cpu/amd/model_lx/msrinit.c"
+#include "cpu/amd/geode_lx/cpureginit.c"
+#include "cpu/amd/geode_lx/syspreinit.c"
+#include "cpu/amd/geode_lx/msrinit.c"
 
 static const u16 sio_init_table[] = { // hi=data, lo=index
 	0x0707,		// select LDN 7 (GPIO, SPI, watchdog, ...)

src/mainboard/lippert/roadrunner-lx/Kconfig

@@ -3,7 +3,7 @@ if BOARD_LIPPERT_ROADRUNNER_LX
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
 	select ARCH_X86
-	select CPU_AMD_LX
+	select CPU_AMD_GEODE_LX
 	select NORTHBRIDGE_AMD_LX
 	select SOUTHBRIDGE_AMD_CS5536
 	select SUPERIO_ITE_IT8712F

src/mainboard/lippert/roadrunner-lx/devicetree.cb

@@ -82,7 +82,7 @@ chip northbridge/amd/lx
   end
   # APIC cluster is late CPU init.
   device lapic_cluster 0 on
-    chip cpu/amd/model_lx
+    chip cpu/amd/geode_lx
       device lapic 0 on end
     end
   end

src/mainboard/lippert/roadrunner-lx/romstage.c

@@ -53,9 +53,9 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
 #include "northbridge/amd/lx/pll_reset.c"
 #include "northbridge/amd/lx/raminit.c"
 #include "lib/generic_sdram.c"
-#include "cpu/amd/model_lx/cpureginit.c"
-#include "cpu/amd/model_lx/syspreinit.c"
-#include "cpu/amd/model_lx/msrinit.c"
+#include "cpu/amd/geode_lx/cpureginit.c"
+#include "cpu/amd/geode_lx/syspreinit.c"
+#include "cpu/amd/geode_lx/msrinit.c"
 
 static const u16 sio_init_table[] = {	// hi=data, lo=index
 	0x0707,		// select LDN 7 (GPIO, SPI, watchdog, ...)

src/mainboard/lippert/spacerunner-lx/Kconfig

@@ -3,7 +3,7 @@ if BOARD_LIPPERT_SPACERUNNER_LX
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
 	select ARCH_X86
-	select CPU_AMD_LX
+	select CPU_AMD_GEODE_LX
 	select NORTHBRIDGE_AMD_LX
 	select SOUTHBRIDGE_AMD_CS5536
 	select SUPERIO_ITE_IT8712F

src/mainboard/lippert/spacerunner-lx/devicetree.cb

@@ -83,7 +83,7 @@ chip northbridge/amd/lx
   end
   # APIC cluster is late CPU init.
   device lapic_cluster 0 on
-    chip cpu/amd/model_lx
+    chip cpu/amd/geode_lx
       device lapic 0 on end
     end
   end

src/mainboard/lippert/spacerunner-lx/romstage.c

@@ -118,9 +118,9 @@ static int smc_send_config(unsigned char config_data)
 #include "northbridge/amd/lx/pll_reset.c"
 #include "northbridge/amd/lx/raminit.c"
 #include "lib/generic_sdram.c"
-#include "cpu/amd/model_lx/cpureginit.c"
-#include "cpu/amd/model_lx/syspreinit.c"
-#include "cpu/amd/model_lx/msrinit.c"
+#include "cpu/amd/geode_lx/cpureginit.c"
+#include "cpu/amd/geode_lx/syspreinit.c"
+#include "cpu/amd/geode_lx/msrinit.c"
 
 static const u16 sio_init_table[] = { // hi=data, lo=index
 	0x0707,		// select LDN 7 (GPIO, SPI, watchdog, ...)

src/mainboard/pcengines/alix1c/Kconfig

@@ -3,7 +3,7 @@ if BOARD_PCENGINES_ALIX1C
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
 	select ARCH_X86
-	select CPU_AMD_LX
+	select CPU_AMD_GEODE_LX
 	select NORTHBRIDGE_AMD_LX
 	select SOUTHBRIDGE_AMD_CS5536
 	select SUPERIO_WINBOND_W83627HF

src/mainboard/pcengines/alix1c/devicetree.cb

@@ -77,7 +77,7 @@ chip northbridge/amd/lx
 
 	# APIC cluster is late CPU init.
 	device lapic_cluster 0 on
-		chip cpu/amd/model_lx
+		chip cpu/amd/geode_lx
 			device lapic 0 on end
 		end
 	end

src/mainboard/pcengines/alix1c/romstage.c

@@ -107,9 +107,9 @@ static u8 spd_read_byte(u8 device, u8 address)
 #include "northbridge/amd/lx/pll_reset.c"
 #include "northbridge/amd/lx/raminit.c"
 #include "lib/generic_sdram.c"
-#include "cpu/amd/model_lx/cpureginit.c"
-#include "cpu/amd/model_lx/syspreinit.c"
-#include "cpu/amd/model_lx/msrinit.c"
+#include "cpu/amd/geode_lx/cpureginit.c"
+#include "cpu/amd/geode_lx/syspreinit.c"
+#include "cpu/amd/geode_lx/msrinit.c"
 
 void main(unsigned long bist)
 {

src/mainboard/pcengines/alix2d/Kconfig

@@ -3,7 +3,7 @@ if BOARD_PCENGINES_ALIX2D
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
 	select ARCH_X86
-	select CPU_AMD_LX
+	select CPU_AMD_GEODE_LX
 	select NORTHBRIDGE_AMD_LX
 	select SOUTHBRIDGE_AMD_CS5536
 	select HAVE_PIRQ_TABLE

src/mainboard/pcengines/alix2d/devicetree.cb

@@ -37,7 +37,7 @@ chip northbridge/amd/lx
 
 	# APIC cluster is late CPU init.
 	device lapic_cluster 0 on
-		chip cpu/amd/model_lx
+		chip cpu/amd/geode_lx
 			device lapic 0 on end
 		end
 	end

src/mainboard/pcengines/alix2d/romstage.c

@@ -106,9 +106,9 @@ static u8 spd_read_byte(u8 device, u8 address)
 #include "northbridge/amd/lx/pll_reset.c"
 #include "northbridge/amd/lx/raminit.c"
 #include "lib/generic_sdram.c"
-#include "cpu/amd/model_lx/cpureginit.c"
-#include "cpu/amd/model_lx/syspreinit.c"
-#include "cpu/amd/model_lx/msrinit.c"
+#include "cpu/amd/geode_lx/cpureginit.c"
+#include "cpu/amd/geode_lx/syspreinit.c"
+#include "cpu/amd/geode_lx/msrinit.c"
 
 /** Early mainboard specific GPIO setup. */
 static void mb_gpio_init(void)

src/mainboard/televideo/tc7020/Kconfig

@@ -21,7 +21,7 @@ if BOARD_TELEVIDEO_TC7020
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
 	select ARCH_X86
-	select CPU_AMD_GX1
+	select CPU_AMD_GEODE_GX1
 	select NORTHBRIDGE_AMD_GX1
 	select SOUTHBRIDGE_AMD_CS5530
 	select SUPERIO_NSC_PC97317

src/mainboard/televideo/tc7020/devicetree.cb

@@ -52,6 +52,6 @@ chip northbridge/amd/gx1		# Northbridge
       register "ide1_enable" = "0"	# Not available/needed on this board
     end
   end
-  chip cpu/amd/model_gx1		# CPU
+  chip cpu/amd/geode_gx1		# CPU
   end
 end

src/mainboard/traverse/geos/Kconfig

@@ -3,7 +3,7 @@ if BOARD_TRAVERSE_GEOS
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
 	select ARCH_X86
-	select CPU_AMD_LX
+	select CPU_AMD_GEODE_LX
 	select NORTHBRIDGE_AMD_LX
 	select SOUTHBRIDGE_AMD_CS5536
 	select HAVE_PIRQ_TABLE

src/mainboard/traverse/geos/devicetree.cb

@@ -33,7 +33,7 @@ chip northbridge/amd/lx
 	end
 	# APIC cluster is late CPU init.
 	device lapic_cluster 0 on
-		chip cpu/amd/model_lx
+		chip cpu/amd/geode_lx
 			device lapic 0 on end
 		end
 	end

src/mainboard/traverse/geos/romstage.c

@@ -47,9 +47,9 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
 #include "northbridge/amd/lx/pll_reset.c"
 #include "northbridge/amd/lx/raminit.c"
 #include "lib/generic_sdram.c"
-#include "cpu/amd/model_lx/cpureginit.c"
-#include "cpu/amd/model_lx/syspreinit.c"
-#include "cpu/amd/model_lx/msrinit.c"
+#include "cpu/amd/geode_lx/cpureginit.c"
+#include "cpu/amd/geode_lx/syspreinit.c"
+#include "cpu/amd/geode_lx/msrinit.c"
 
 void main(unsigned long bist)
 {

src/mainboard/winent/pl6064/Kconfig

@@ -3,7 +3,7 @@ if BOARD_WINENT_PL6064
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
 	select ARCH_X86
-	select CPU_AMD_LX
+	select CPU_AMD_GEODE_LX
 	select NORTHBRIDGE_AMD_LX
 	select SOUTHBRIDGE_AMD_CS5536
 	select SUPERIO_WINBOND_W83627HF

src/mainboard/winent/pl6064/devicetree.cb

@@ -73,7 +73,7 @@ chip northbridge/amd/lx
 	end
 	# APIC cluster is late CPU init.
 	device lapic_cluster 0 on
-		chip cpu/amd/model_lx
+		chip cpu/amd/geode_lx
 			device lapic 0 on end
 		end
 	end

src/mainboard/winent/pl6064/romstage.c

@@ -51,9 +51,9 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
 #include "northbridge/amd/lx/pll_reset.c"
 #include "northbridge/amd/lx/raminit.c"
 #include "lib/generic_sdram.c"
-#include "cpu/amd/model_lx/cpureginit.c"
-#include "cpu/amd/model_lx/syspreinit.c"
-#include "cpu/amd/model_lx/msrinit.c"
+#include "cpu/amd/geode_lx/cpureginit.c"
+#include "cpu/amd/geode_lx/syspreinit.c"
+#include "cpu/amd/geode_lx/msrinit.c"
 
 void main(unsigned long bist)
 {

src/mainboard/wyse/s50/Kconfig

@@ -21,7 +21,7 @@ if BOARD_WYSE_S50
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
 	select ARCH_X86
-	select CPU_AMD_GX2
+	select CPU_AMD_GEODE_GX2
 	select NORTHBRIDGE_AMD_GX2
 	select SOUTHBRIDGE_AMD_CS5536
 	select UDELAY_TSC

src/mainboard/wyse/s50/devicetree.cb

@@ -44,7 +44,7 @@ chip northbridge/amd/gx2
 	end
 	# APIC cluster is late CPU init.
 	device lapic_cluster 0 on
-		chip cpu/amd/model_gx2
+		chip cpu/amd/geode_gx2
 			device lapic 0 on end
 		end
 	end

src/mainboard/wyse/s50/romstage.c

@@ -45,9 +45,9 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
 #include "northbridge/amd/gx2/pll_reset.c"
 #include "northbridge/amd/gx2/raminit.c"
 #include "lib/generic_sdram.c"
-#include "cpu/amd/model_gx2/cpureginit.c"
-#include "cpu/amd/model_gx2/syspreinit.c"
-#include "cpu/amd/model_lx/msrinit.c"
+#include "cpu/amd/geode_gx2/cpureginit.c"
+#include "cpu/amd/geode_gx2/syspreinit.c"
+#include "cpu/amd/geode_lx/msrinit.c"
 
 void main(unsigned long bist)
 {