GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

soc/intel/skylake: Pass proper CPU flex ratio override to FSP 

In bootblock, cpu flex ratio is set to non-turbo max.

In FSP UPD, if CpuRatioOverride is zero, then it tries to program cpu
ratio to zero. Since it is different than the non-zero value programmed
in bootblock, FSP gives reset.

To avoid the reset, set FSP UPD for CPU flex ratio override to that
value as set in bootblock.

Change-Id: I8cae5530ec97cedfbd71771f291db6f55a9fd5c2
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/17555
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Naresh G Solanki 2016-11-16 21:34:41 +05:30 committed by Aaron Durbin
parent 09fa0391f5
commit 79239b75a7
1 changed files with 16 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
src/soc/intel/skylake/romstage/romstage_fsp20.c
View File

@ -19,12 +19,14 @@
#include <arch/symbols.h>
#include <assert.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/msr.h>
#include <cbmem.h>
#include <chip.h>
#include <console/console.h>
#include <device/pci_def.h>
#include <fsp/util.h>
#include <fsp/memmap.h>
#include <soc/msr.h>
#include <soc/pci_devs.h>
#include <soc/pm.h>
#include <soc/romstage.h>
@ -94,6 +96,18 @@ asmlinkage void *car_stage_c_entry(void)
return postcar_commit_mtrrs(&pcf);
}
static void cpu_flex_override(FSP_M_CONFIG *m_cfg)
{
msr_t flex_ratio;
m_cfg->CpuRatioOverride = 1;
/*
* Set cpuratio to that value set in bootblock, This will ensure FSPM
* knows the intended flex ratio.
*/
flex_ratio = rdmsr(MSR_FLEX_RATIO);
m_cfg->CpuRatio = (flex_ratio.lo >> 8) & 0xff;
}
static void soc_memory_init_params(FSP_M_CONFIG *m_cfg)
{
const struct device *dev;
@ -130,6 +144,8 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg)
mask |= (1<<i);
}
m_cfg->PcieRpEnableMask = mask;
cpu_flex_override(m_cfg);
}
void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)