clean up LD scripts and add some comments and proper license headers
where applicable. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5419 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
parent
ea7f5a253b
commit
79253841a7
|
@ -1,11 +1,12 @@
|
|||
/*
|
||||
* Memory map:
|
||||
*
|
||||
* CONFIG_RAMBASE
|
||||
* CONFIG_RAMBASE : text segment
|
||||
* : rodata segment
|
||||
* : data segment
|
||||
* : bss segment
|
||||
* : heap
|
||||
* : stack
|
||||
* : heap
|
||||
*/
|
||||
/*
|
||||
* Bootstrap code for the STPC Consumer
|
||||
|
@ -17,10 +18,8 @@
|
|||
* Rewritten by Eric Biederman
|
||||
* 2005.12 yhlu add coreboot_ram cross the vga font buffer handling
|
||||
*/
|
||||
/*
|
||||
* We use ELF as output format. So that we can
|
||||
* debug the code in some form.
|
||||
*/
|
||||
|
||||
/* We use ELF as output format. So that we can debug the code in some form. */
|
||||
INCLUDE ldoptions
|
||||
|
||||
ENTRY(_start)
|
||||
|
@ -28,9 +27,8 @@ ENTRY(_start)
|
|||
SECTIONS
|
||||
{
|
||||
. = CONFIG_RAMBASE;
|
||||
/*
|
||||
* First we place the code and read only data (typically const declared).
|
||||
* This get placed in rom.
|
||||
/* First we place the code and read only data (typically const declared).
|
||||
* This could theoretically be placed in rom.
|
||||
*/
|
||||
.text : {
|
||||
_text = .;
|
||||
|
@ -39,6 +37,7 @@ SECTIONS
|
|||
. = ALIGN(16);
|
||||
_etext = .;
|
||||
}
|
||||
|
||||
.rodata : {
|
||||
_rodata = .;
|
||||
. = ALIGN(4);
|
||||
|
@ -54,17 +53,14 @@ SECTIONS
|
|||
ecpu_drivers = . ;
|
||||
*(.rodata)
|
||||
*(.rodata.*)
|
||||
/*
|
||||
* kevinh/Ispiri - Added an align, because the objcopy tool
|
||||
/* kevinh/Ispiri - Added an align, because the objcopy tool
|
||||
* incorrectly converts sections that are not long word aligned.
|
||||
* This breaks the coreboot.rom target.
|
||||
*/
|
||||
. = ALIGN(4);
|
||||
|
||||
_erodata = .;
|
||||
}
|
||||
/*
|
||||
* After the code we place initialized data (typically initialized
|
||||
/* After the code we place initialized data (typically initialized
|
||||
* global variables). This gets copied into ram by startup code.
|
||||
* __data_start and __data_end shows where in ram this should be placed,
|
||||
* whereas __data_loadstart and __data_loadend shows where in rom to
|
||||
|
@ -76,18 +72,7 @@ SECTIONS
|
|||
_edata = .;
|
||||
}
|
||||
|
||||
.sdata : {
|
||||
_SDA_BASE_ = .;
|
||||
*(.sdata)
|
||||
}
|
||||
|
||||
.sdata2 : {
|
||||
_SDA2_BASE_ = .;
|
||||
*(.sdata2)
|
||||
}
|
||||
|
||||
/*
|
||||
* bss does not contain data, it is just a space that should be zero
|
||||
/* bss does not contain data, it is just a space that should be zero
|
||||
* initialized on startup. (typically uninitialized global variables)
|
||||
* crt0.S fills between _bss and _ebss with zeroes.
|
||||
*/
|
||||
|
@ -99,6 +84,11 @@ SECTIONS
|
|||
}
|
||||
_ebss = .;
|
||||
_end = .;
|
||||
|
||||
/* coreboot really "ends" here. Only heap and stack are placed after
|
||||
* this line.
|
||||
*/
|
||||
|
||||
. = ALIGN(CONFIG_STACK_SIZE);
|
||||
|
||||
_stack = .;
|
||||
|
@ -107,6 +97,7 @@ SECTIONS
|
|||
. += CONFIG_MAX_CPUS*CONFIG_STACK_SIZE;
|
||||
}
|
||||
_estack = .;
|
||||
|
||||
_heap = .;
|
||||
.heap . : {
|
||||
/* Reserve CONFIG_HEAP_SIZE bytes for the heap */
|
||||
|
@ -115,18 +106,33 @@ SECTIONS
|
|||
}
|
||||
_eheap = .;
|
||||
|
||||
/* Some assertions to print human readable errors for certain linker
|
||||
* error scenarios.
|
||||
*/
|
||||
|
||||
/* Avoid running into 0xa0000-0xfffff */
|
||||
_bogus = ASSERT(CONFIG_RAMBASE >= 0x100000 || _eheap < 0xa0000, "Please move RAMBASE to 1MB");
|
||||
|
||||
/* The ram segment
|
||||
* This is all address of the memory resident copy of coreboot.
|
||||
/* The ram segment. This includes all memory used by the memory
|
||||
* resident copy of coreboot, except the tables that are produced on
|
||||
* the fly, but including stack and heap.
|
||||
*/
|
||||
_ram_seg = _text;
|
||||
_eram_seg = _eheap;
|
||||
|
||||
_bogus = ASSERT( ( _eram_seg < (CONFIG_RAMTOP)) , "please increase CONFIG_RAMTOP");
|
||||
/* CONFIG_RAMTOP is the upper address of cached memory (among other
|
||||
* things). We must not exceed beyond that address, there be dragons.
|
||||
*/
|
||||
_bogus = ASSERT( ( _eram_seg < (CONFIG_RAMTOP)) , "Please increase CONFIG_RAMTOP");
|
||||
|
||||
_bogus = ASSERT( !((CONFIG_CONSOLE_VGA || CONFIG_PCI_ROM_RUN) && ((_ram_seg<0xa0000) && (_eram_seg>0xa0000))) , "please increase CONFIG_RAMTOP and if still fail, try to set CONFIG_RAMBASE more than 1M");
|
||||
/* This rule is only good for the few broken targets that still live
|
||||
* below 1MB per default. Those are the Geode and VIA targets that come
|
||||
* with their own version of real mode switches that can't live above
|
||||
* 1MB. Once these are fixed, this rule should go away.
|
||||
*/
|
||||
_bogus = ASSERT( !((CONFIG_CONSOLE_VGA || CONFIG_PCI_ROM_RUN || CONFIG_VGA_ROM_RUN || CONFIG_HAVE_SMI_HANDLER) && ((_ram_seg<0xa0000) && (_eram_seg>0xa0000))), "Please increase CONFIG_RAMTOP and if still fail, try to set CONFIG_RAMBASE to 1M");
|
||||
|
||||
/* Discard the sections we don't need/want */
|
||||
|
||||
/DISCARD/ : {
|
||||
*(.comment)
|
||||
|
|
|
@ -1,4 +1,23 @@
|
|||
/* INPUT(coreboot_ap.rom)*/
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2006 Advanced Micro Devices, Inc.
|
||||
* Copyright (C) 2008-2010 coresystems GmbH
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
INCLUDE "ldoptions"
|
||||
SECTIONS
|
||||
{
|
||||
|
@ -9,8 +28,4 @@ SECTIONS
|
|||
*(.rodata.*)
|
||||
_eapcrom = .;
|
||||
}
|
||||
_iseg_apc = CONFIG_DCACHE_RAM_BASE;
|
||||
_eiseg_apc = _iseg_apc + SIZEOF(.apcrom);
|
||||
_liseg_apc = _apcrom;
|
||||
_eliseg_apc = _eapcrom;
|
||||
}
|
||||
|
|
|
@ -1,29 +1,24 @@
|
|||
/*
|
||||
* Memory map:
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* CONFIG_RAMBASE
|
||||
* : data segment
|
||||
* : bss segment
|
||||
* : heap
|
||||
* : stack
|
||||
* CONFIG_ROMBASE
|
||||
* : coreboot text
|
||||
* : readonly text
|
||||
*/
|
||||
/*
|
||||
* Bootstrap code for the STPC Consumer
|
||||
* Copyright (c) 1999 by Net Insight AB. All Rights Reserved.
|
||||
* Copyright (C) 2006 Advanced Micro Devices, Inc.
|
||||
* Copyright (C) 2008-2010 coresystems GmbH
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* Written by Johan Rydberg, based on work by Daniel Kahlin.
|
||||
* Rewritten by Eric Biederman
|
||||
*/
|
||||
/*
|
||||
* We use ELF as output format. So that we can
|
||||
* debug the code in some form.
|
||||
*/
|
||||
/* We use ELF as output format. So that we can debug the code in some form. */
|
||||
OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386")
|
||||
OUTPUT_ARCH(i386)
|
||||
|
||||
|
@ -34,8 +29,6 @@ MEMORY {
|
|||
TARGET(binary)
|
||||
SECTIONS
|
||||
{
|
||||
. = 0;
|
||||
|
||||
/* This section might be better named .setup */
|
||||
.rom ROMLOC : {
|
||||
_rom = .;
|
||||
|
|
|
@ -1,36 +1,27 @@
|
|||
/*
|
||||
* Memory map:
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* CONFIG_RAMBASE
|
||||
* : data segment
|
||||
* : bss segment
|
||||
* : heap
|
||||
* : stack
|
||||
* CONFIG_ROMBASE
|
||||
* : coreboot text
|
||||
* : readonly text
|
||||
*/
|
||||
/*
|
||||
* Bootstrap code for the STPC Consumer
|
||||
* Copyright (c) 1999 by Net Insight AB. All Rights Reserved.
|
||||
* Copyright (C) 2006 Advanced Micro Devices, Inc.
|
||||
* Copyright (C) 2008-2010 coresystems GmbH
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* Written by Johan Rydberg, based on work by Daniel Kahlin.
|
||||
* Rewritten by Eric Biederman
|
||||
*/
|
||||
/*
|
||||
* We use ELF as output format. So that we can
|
||||
* debug the code in some form.
|
||||
*/
|
||||
/* We use ELF as output format. So that we can debug the code in some form. */
|
||||
OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386")
|
||||
OUTPUT_ARCH(i386)
|
||||
|
||||
/*
|
||||
ENTRY(_start)
|
||||
*/
|
||||
|
||||
TARGET(binary)
|
||||
SECTIONS
|
||||
{
|
||||
|
@ -45,8 +36,6 @@ SECTIONS
|
|||
_rom = .;
|
||||
*(.rom.text);
|
||||
*(.rom.data);
|
||||
*(.init.rodata.*);
|
||||
*(.init.text);
|
||||
*(.rodata);
|
||||
*(.rodata.*);
|
||||
*(.rom.data.*);
|
||||
|
|
Loading…
Reference in New Issue