soc/intel/tigerlake: Correct IRQ interrupt
Current Interrupt setting use 2nd parameters as device function number.
- Correct as interrupt pin number according to _PRT package format.
{Address, pin, Source, Source index}
- Use irq number directly rather than irq definition as its number
is not for PCI device.
The issue found while enabling GBE and GBE interrupt is not working
without this change.
Reference
- ACPI spec 6.2.13 _PRT
- FSP reference code:
https://github.com/otcshare/CCG-TGL-Generic-SiC/blob/TGL.3163.01/
ClientOneSiliconPkg/IpBlock/Itss/LibraryPrivate/PeiItssPolicyLib/
PeiItssPolicyLibVer2.c
- BIOS reference code:
https://github.com/otcshare/CCG-TGL-Generic-Full/blob/master/
TigerLakeBoardPkg/Acpi/AcpiTables/Dsdt/PciTree.asl
TEST=boot to OS with GBE enabled and check GBE interrupt
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I8084b30c668c155ebabbee90b5f70054813b328e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41153
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Wonkyu Kim
Patrick Georgi
parent
04953ebf5f
commit
79412ed364
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@ -1,146 +1,152 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <soc/irq.h>
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Name (PICP, Package () {
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Name (PICP, Package () {
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/* D31:HDA, SMBUS, TraceHUB */
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/* D31 */
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Package(){0x001FFFFF, 3, 0, HDA_IRQ },
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Package(){0x001FFFFF, 0, 0, 16 },
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Package(){0x001FFFFF, 4, 0, SMBUS_IRQ },
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/* D30 */
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Package(){0x001FFFFF, 6, 0, GBE_IRQ },
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Package(){0x001EFFFF, 0, 0, 16 },
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Package(){0x001FFFFF, 7, 0, TRACEHUB_IRQ },
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Package(){0x001EFFFF, 1, 0, 17 },
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/* D30: UART0, UART1, SPI0, SPI1 */
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Package(){0x001EFFFF, 2, 0, 36 },
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Package(){0x001EFFFF, 0, 0, LPSS_UART0_IRQ },
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Package(){0x001EFFFF, 3, 0, 37 },
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Package(){0x001EFFFF, 1, 0, LPSS_UART1_IRQ },
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/* D29 */
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Package(){0x001EFFFF, 2, 0, LPSS_SPI0_IRQ },
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Package(){0x001DFFFF, 0, 0, 16 },
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Package(){0x001EFFFF, 3, 0, LPSS_SPI1_IRQ },
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Package(){0x001DFFFF, 1, 0, 17 },
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/* D29: RP9 ~ RP12 */
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Package(){0x001DFFFF, 2, 0, 18 },
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Package(){0x001DFFFF, 0, 0, PCIE_9_IRQ },
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Package(){0x001DFFFF, 3, 0, 19 },
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Package(){0x001DFFFF, 1, 0, PCIE_10_IRQ },
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/* D28 */
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Package(){0x001DFFFF, 2, 0, PCIE_11_IRQ },
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Package(){0x001CFFFF, 0, 0, 16 },
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Package(){0x001DFFFF, 3, 0, PCIE_12_IRQ },
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Package(){0x001CFFFF, 1, 0, 17 },
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/* D28: RP1 ~ RP8 */
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Package(){0x001CFFFF, 2, 0, 18 },
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Package(){0x001CFFFF, 0, 0, PCIE_1_IRQ },
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Package(){0x001CFFFF, 3, 0, 19 },
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Package(){0x001CFFFF, 1, 0, PCIE_2_IRQ },
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/* D25 */
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Package(){0x001CFFFF, 2, 0, PCIE_3_IRQ },
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Package(){0x0019FFFF, 0, 0, 31 },
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Package(){0x001CFFFF, 3, 0, PCIE_4_IRQ },
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Package(){0x0019FFFF, 1, 0, 32 },
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Package(){0x001CFFFF, 4, 0, PCIE_5_IRQ },
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Package(){0x0019FFFF, 2, 0, 33 },
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Package(){0x001CFFFF, 5, 0, PCIE_6_IRQ },
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/* D23 */
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Package(){0x001CFFFF, 6, 0, PCIE_7_IRQ },
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Package(){0x0017FFFF, 0, 0, 16 },
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Package(){0x001CFFFF, 7, 0, PCIE_8_IRQ },
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/* D22 */
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/* D25: I2C4, I2C5, UART2 */
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Package(){0x0016FFFF, 0, 0, 16 },
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Package(){0x0019FFFF, 0, 0, LPSS_I2C4_IRQ },
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Package(){0x0016FFFF, 1, 0, 17 },
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Package(){0x0019FFFF, 1, 0, LPSS_I2C5_IRQ },
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Package(){0x0016FFFF, 2, 0, 18 },
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Package(){0x0019FFFF, 2, 0, LPSS_UART2_IRQ },
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Package(){0x0016FFFF, 3, 0, 19 },
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/* D23: SATA */
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/* D21 */
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Package(){0x0017FFFF, 0, 0, SATA_IRQ },
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Package(){0x0015FFFF, 0, 0, 27 },
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/* D22: CSME */
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Package(){0x0015FFFF, 1, 0, 40 },
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Package(){0x0016FFFF, 0, 0, HECI_1_IRQ },
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Package(){0x0015FFFF, 2, 0, 29 },
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Package(){0x0016FFFF, 1, 0, HECI_2_IRQ },
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Package(){0x0015FFFF, 3, 0, 30 },
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Package(){0x0016FFFF, 4, 0, HECI_3_IRQ },
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/* D20 */
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Package(){0x0016FFFF, 5, 0, HECI_4_IRQ },
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Package(){0x0014FFFF, 0, 0, 16 },
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/* D21: I2C0 ~ I2C3 */
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Package(){0x0014FFFF, 1, 0, 17 },
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Package(){0x0015FFFF, 0, 0, LPSS_I2C0_IRQ },
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/* D19 */
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Package(){0x0015FFFF, 1, 0, LPSS_I2C1_IRQ },
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Package(){0x0013FFFF, 0, 0, 43 },
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Package(){0x0015FFFF, 2, 0, LPSS_I2C2_IRQ },
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Package(){0x0013FFFF, 1, 0, 24 },
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Package(){0x0015FFFF, 3, 0, LPSS_I2C3_IRQ },
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Package(){0x0013FFFF, 2, 0, 25 },
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/* D20: xHCI, xDCI, SRAM, CNVI_WIFI */
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Package(){0x0013FFFF, 3, 0, 38 },
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Package(){0x0014FFFF, 0, 0, xHCI_IRQ },
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/* D18 */
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Package(){0x0014FFFF, 1, 0, xDCI_IRQ },
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Package(){0x0012FFFF, 0, 0, 16 },
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Package(){0x0014FFFF, 3, 0, CNVI_WIFI_IRQ },
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Package(){0x0012FFFF, 1, 0, 34 },
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/* D19: SPI3 */
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/* D17 */
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Package(){0x0013FFFF, 0, 0, LPSS_SPI3_IRQ },
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Package(){0x0011FFFF, 0, 0, 35 },
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/* D18: ISH, SPI2 */
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Package(){0x0011FFFF, 1, 0, 20 },
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Package(){0x0012FFFF, 0, 0, ISH_IRQ },
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Package(){0x0011FFFF, 2, 0, 21 },
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Package(){0x0012FFFF, 6, 0, LPSS_SPI2_IRQ },
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Package(){0x0011FFFF, 3, 0, 42 },
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/* D16: TCH0, TCH1 */
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/* D16 */
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Package(){0x0010FFFF, 6, 0, THC0_IRQ },
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Package(){0x0010FFFF, 0, 0, 23 },
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Package(){0x0010FFFF, 7, 0, THC1_IRQ },
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Package(){0x0010FFFF, 1, 0, 22 },
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/* D13: xHCI, xDCI */
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Package(){0x0010FFFF, 2, 0, 18 },
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Package(){0x000DFFFF, 0, 0, xHCI_IRQ },
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Package(){0x0010FFFF, 3, 0, 19 },
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Package(){0x000DFFFF, 1, 0, xDCI_IRQ },
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/* D13 */
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/* D8: GNA */
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Package(){0x000DFFFF, 0, 0, 16 },
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Package(){0x0008FFFF, 0, 0, GNA_IRQ },
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Package(){0x000DFFFF, 1, 0, 17 },
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/* D7: TBT PCIe */
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/* D8 */
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Package(){0x0007FFFF, 0, 0, TBT_PCIe0_IRQ },
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Package(){0x0008FFFF, 0, 0, 16 },
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Package(){0x0007FFFF, 1, 0, TBT_PCIe1_IRQ },
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/* D7 */
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Package(){0x0007FFFF, 2, 0, TBT_PCIe2_IRQ },
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Package(){0x0007FFFF, 0, 0, 16 },
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Package(){0x0007FFFF, 3, 0, TBT_PCIe3_IRQ },
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Package(){0x0007FFFF, 1, 0, 17 },
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/* D6: PEG60 */
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Package(){0x0007FFFF, 2, 0, 18 },
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Package(){0x0006FFFF, 0, 0, PEG_IRQ },
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Package(){0x0007FFFF, 3, 0, 19 },
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/* D5: IPU Device */
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/* D6 */
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Package(){0x0005FFFF, 0, 0, IPU_IRQ },
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Package(){0x0006FFFF, 0, 0, 16 },
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/* D4: Thermal Device */
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/* D5 */
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Package(){0x0004FFFF, 0, 0, THERMAL_IRQ },
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Package(){0x0005FFFF, 0, 0, 16 },
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/* D2: IGFX */
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/* D4 */
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Package(){0x0002FFFF, 0, 0, IGFX_IRQ },
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Package(){0x0004FFFF, 0, 0, 16 },
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/* D2 */
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Package(){0x0002FFFF, 0, 0, 16 },
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})
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})
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Name (PICN, Package () {
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Name (PICN, Package () {
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/* D31:HDA, SMBUS, TraceHUB*/
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/* D31 */
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Package () { 0x001FFFFF, 3, 0, 11 },
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Package(){0x001FFFFF, 0, 0, 11 },
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Package () { 0x001FFFFF, 4, 0, 11 },
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/* D30 */
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Package () { 0x001FFFFF, 7, 0, 11 },
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Package(){0x001EFFFF, 0, 0, 11 },
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/* D30: UART0, UART1, SPI0, SPI1 */
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Package(){0x001EFFFF, 1, 0, 10 },
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Package () { 0x001EFFFF, 0, 0, 11 },
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Package(){0x001EFFFF, 2, 0, 11 },
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Package () { 0x001EFFFF, 1, 0, 10 },
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Package(){0x001EFFFF, 3, 0, 11 },
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Package () { 0x001EFFFF, 2, 0, 11 },
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/* D29 */
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Package () { 0x001EFFFF, 3, 0, 11 },
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Package(){0x001DFFFF, 0, 0, 11 },
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/* D29: RP9 ~ RP12 */
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Package(){0x001DFFFF, 1, 0, 10 },
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Package () { 0x001DFFFF, 0, 0, 11 },
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Package(){0x001DFFFF, 2, 0, 11 },
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Package () { 0x001DFFFF, 1, 0, 10 },
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Package(){0x001DFFFF, 3, 0, 11 },
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Package () { 0x001DFFFF, 2, 0, 11 },
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/* D28 */
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Package () { 0x001DFFFF, 3, 0, 11 },
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Package(){0x001CFFFF, 0, 0, 11 },
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/* D28: RP1 ~ RP8 */
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Package(){0x001CFFFF, 1, 0, 10 },
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Package () { 0x001CFFFF, 0, 0, 11 },
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Package(){0x001CFFFF, 2, 0, 11 },
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Package () { 0x001CFFFF, 1, 0, 10 },
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Package(){0x001CFFFF, 3, 0, 11 },
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Package () { 0x001CFFFF, 2, 0, 11 },
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/* D25 */
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Package () { 0x001CFFFF, 3, 0, 11 },
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Package () { 0x001CFFFF, 4, 0, 11 },
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Package () { 0x001CFFFF, 5, 0, 10 },
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Package () { 0x001CFFFF, 6, 0, 11 },
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Package () { 0x001CFFFF, 7, 0, 11 },
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/* D25: I2C4, I2C5, UART2 */
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Package(){0x0019FFFF, 0, 0, 11 },
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Package(){0x0019FFFF, 0, 0, 11 },
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Package(){0x0019FFFF, 1, 0, 10 },
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Package(){0x0019FFFF, 1, 0, 10 },
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Package(){0x0019FFFF, 2, 0, 11 },
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Package(){0x0019FFFF, 2, 0, 11 },
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/* D23: SATA */
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/* D23 */
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Package () { 0x0017FFFF, 0, 0, 11 },
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Package(){0x0017FFFF, 0, 0, 11 },
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/* D22: CSME */
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/* D22 */
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Package(){0x0016FFFF, 0, 0, 11 },
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Package(){0x0016FFFF, 0, 0, 11 },
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Package(){0x0016FFFF, 1, 0, 10 },
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Package(){0x0016FFFF, 1, 0, 10 },
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Package(){0x0016FFFF, 4, 0, 11 },
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Package(){0x0016FFFF, 2, 0, 11 },
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Package(){0x0016FFFF, 5, 0, 11 },
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Package(){0x0016FFFF, 3, 0, 11 },
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/* D21: I2C0 ~ I2C3 */
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/* D21 */
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Package(){0x0015FFFF, 0, 0, 11 },
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Package(){0x0015FFFF, 0, 0, 11 },
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Package(){0x0015FFFF, 1, 0, 10 },
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Package(){0x0015FFFF, 1, 0, 10 },
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Package(){0x0015FFFF, 2, 0, 11 },
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Package(){0x0015FFFF, 2, 0, 11 },
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Package(){0x0015FFFF, 3, 0, 11 },
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Package(){0x0015FFFF, 3, 0, 11 },
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/* D19: SPI3 */
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/* D20 */
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Package(){0x0014FFFF, 0, 0, 11 },
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Package(){0x0014FFFF, 0, 0, 10 },
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/* D19 */
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Package(){0x0013FFFF, 0, 0, 11 },
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Package(){0x0013FFFF, 0, 0, 11 },
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/* D18: ISH, SPI2 */
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Package(){0x0013FFFF, 1, 0, 10 },
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Package(){0x0013FFFF, 2, 0, 11 },
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Package(){0x0013FFFF, 3, 0, 11 },
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/* D18 */
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Package(){0x0012FFFF, 0, 0, 11 },
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Package(){0x0012FFFF, 0, 0, 11 },
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Package(){0x0012FFFF, 6, 0, 11 },,
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Package(){0x0012FFFF, 1, 0, 10 },,
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/* D16: CNVI_BT, TCH0, TCH1 */
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/* D18 */
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Package(){0x0011FFFF, 0, 0, 11 },
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Package(){0x0011FFFF, 1, 0, 10 },
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Package(){0x0011FFFF, 2, 0, 11 },
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Package(){0x0011FFFF, 3, 0, 11 },
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/* D16 */
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Package(){0x0010FFFF, 0, 0, 11 },
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Package(){0x0010FFFF, 1, 0, 10 },
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Package(){0x0010FFFF, 2, 0, 11 },
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Package(){0x0010FFFF, 2, 0, 11 },
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Package(){0x0010FFFF, 6, 0, 11 },
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Package(){0x0010FFFF, 3, 0, 11 },
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Package(){0x0010FFFF, 7, 0, 10 },
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/* D13 */
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/* D13: xHCI, xDCI */
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Package(){0x000DFFFF, 0, 0, 11 },
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Package(){0x000DFFFF, 0, 0, 11 },
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Package(){0x000DFFFF, 1, 0, 10 },
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Package(){0x000DFFFF, 1, 0, 10 },
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/* D8: GNA */
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/* D8 */
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Package(){0x0008FFFF, 0, 0, 11 },
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Package(){0x0008FFFF, 0, 0, 11 },
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/* D7: TBT PCIe */
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/* D7 */
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Package(){0x0007FFFF, 0, 0, 11 },
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Package(){0x0007FFFF, 0, 0, 11 },
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Package(){0x0007FFFF, 1, 0, 10 },
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Package(){0x0007FFFF, 1, 0, 10 },
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Package(){0x0007FFFF, 2, 0, 11 },
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Package(){0x0007FFFF, 2, 0, 11 },
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Package(){0x0007FFFF, 3, 0, 11 },
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Package(){0x0007FFFF, 3, 0, 11 },
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/* D6: PEG60 */
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/* D6 */
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Package(){0x0006FFFF, 0, 0, 11 },
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Package(){0x0006FFFF, 0, 0, 11 },
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/* D5: IPU Device */
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/* D5 */
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Package(){0x0005FFFF, 0, 0, 11 },
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Package(){0x0005FFFF, 0, 0, 11 },
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/* D4: Thermal Device */
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/* D4 */
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Package(){0x0004FFFF, 0, 0, 11 },
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Package(){0x0004FFFF, 0, 0, 11 },
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/* D2: IGFX */
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/* D2 */
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Package(){0x0002FFFF, 0, 0, 11 },
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Package(){0x0002FFFF, 0, 0, 11 },
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})
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})
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@ -9,64 +9,4 @@
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#define PCH_IRQ10 10
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#define PCH_IRQ10 10
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#define PCH_IRQ11 11
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#define PCH_IRQ11 11
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#define LPSS_I2C0_IRQ 27
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#define LPSS_I2C1_IRQ 40
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#define LPSS_I2C2_IRQ 29
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#define LPSS_I2C3_IRQ 30
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#define LPSS_I2C4_IRQ 31
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#define LPSS_I2C5_IRQ 32
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#define LPSS_SPI0_IRQ 36
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#define LPSS_SPI1_IRQ 37
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#define LPSS_SPI2_IRQ 34
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#define LPSS_SPI3_IRQ 43
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#define LPSS_UART0_IRQ 16
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#define LPSS_UART1_IRQ 17
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#define LPSS_UART2_IRQ 33
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#define HDA_IRQ 16
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#define GBE_IRQ 16
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#define SMBUS_IRQ 16
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#define TRACEHUB_IRQ 16
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#define PCIE_1_IRQ 16
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#define PCIE_2_IRQ 17
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#define PCIE_3_IRQ 18
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#define PCIE_4_IRQ 19
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#define PCIE_5_IRQ 16
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#define PCIE_6_IRQ 17
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#define PCIE_7_IRQ 18
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#define PCIE_8_IRQ 19
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#define PCIE_9_IRQ 16
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#define PCIE_10_IRQ 17
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#define PCIE_11_IRQ 18
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#define PCIE_12_IRQ 19
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#define SATA_IRQ 16
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#define xHCI_IRQ 16
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#define xDCI_IRQ 17
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#define CNVI_WIFI_IRQ 16
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#define CNVI_BT_IRQ 18
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#define THC0_IRQ 23
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#define THC1_IRQ 22
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#define ISH_IRQ 16
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#define TBT_PCIe0_IRQ 16
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#define TBT_PCIe1_IRQ 17
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#define TBT_PCIe2_IRQ 18
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#define TBT_PCIe3_IRQ 19
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#define HECI_1_IRQ 16
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#define HECI_2_IRQ 17
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#define HECI_3_IRQ 16
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#define HECI_4_IRQ 19
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#define PEG_IRQ 16
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#define IGFX_IRQ 16
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#define THERMAL_IRQ 16
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#define IPU_IRQ 16
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#define GNA_IRQ 16
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#endif /* _SOC_IRQ_H_ */
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#endif /* _SOC_IRQ_H_ */
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