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soc/intel/meteorlake: Enable V1p05-PHY supply external FET control 

This patch enables S0i2.2 by letting 1.5V Phy supply to control the
externa FET.

BUG=b:256805904

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I8771c11ce3b305343c7e96510e1375538d5e7f04
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72709
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
This commit is contained in:
Subrata Banik 2023-02-01 17:19:50 +05:30 committed by Sridhar Siricilla
parent b184e6e0a1
commit 794137e2a8
1 changed files with 1 additions and 0 deletions
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1
src/soc/intel/meteorlake/fsp_params.c
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@ -643,6 +643,7 @@ static void fill_fsps_misc_power_params(FSP_S_CONFIG *s_cfg,
s_cfg->EnergyEfficientTurbo = 1; s_cfg->EnergyEfficientTurbo = 1;
s_cfg->PmcLpmS0ixSubStateEnableMask = get_supported_lpm_mask(); s_cfg->PmcLpmS0ixSubStateEnableMask = get_supported_lpm_mask();
s_cfg->PkgCStateDemotion = !config->disable_package_c_state_demotion; s_cfg->PkgCStateDemotion = !config->disable_package_c_state_demotion;
s_cfg->PmcV1p05PhyExtFetControlEn = 1;
} }