soc/intel/apollolake: Clean up code by using common System Agent module
This patch currently contains the SA initialization required for bootblock phase - 1. Use SOC_INTEL_COMMON_BLOCK_SA kconfig for common SA code. 2. Perform PCIEXBAR programming based on soc configurable PCIEX_LENGTH_xxxMB 3. Use common systemagent header file. Change-Id: I01a24e2d4f1c8c9ca113c128bb6b3eac23dc79ad Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/18567 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
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@ -41,6 +41,7 @@ config CPU_SPECIFIC_OPTIONS
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select PCIEXP_COMMON_CLOCK
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select PCIEXP_CLK_PM
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select PCIEXP_L1_SUB_STATE
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select PCIEX_LENGTH_256MB
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select POSTCAR_CONSOLE
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select POSTCAR_STAGE
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select REG_SCRIPT
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@ -51,6 +52,7 @@ config CPU_SPECIFIC_OPTIONS
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select SOC_INTEL_COMMON_ACPI
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select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
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select SOC_INTEL_COMMON_BLOCK
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select SOC_INTEL_COMMON_BLOCK_SA
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select SOC_INTEL_COMMON_LPSS_I2C
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select SOC_INTEL_COMMON_SMI
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select SOC_INTEL_COMMON_SPI_FLASH_PROTECT
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@ -89,10 +91,6 @@ config SOC_INTEL_COMMON_RESET
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bool
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default y
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config MMCONF_BASE_ADDRESS
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hex "PCI MMIO Base Address"
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default 0xe0000000
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config IOSF_BASE_ADDRESS
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hex "MMIO Base Address of sideband bus"
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default 0xd0000000
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@ -283,7 +281,7 @@ config USE_APOLLOLAKE_FSP_CAR
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bool "Use FSP CAR"
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select FSP_CAR
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help
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Use FSP APIs to initialize & tear Down the Cache-As-Ram.
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Use FSP APIs to initialize & tear down the Cache-As-Ram.
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endchoice
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@ -18,6 +18,7 @@
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#include <bootblock_common.h>
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#include <cpu/x86/mtrr.h>
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#include <device/pci.h>
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#include <intelblocks/systemagent.h>
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#include <lib.h>
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#include <soc/iomap.h>
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#include <soc/cpu.h>
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@ -25,7 +26,7 @@
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#include <soc/gpio.h>
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#include <soc/iosf.h>
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#include <soc/mmap_boot.h>
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#include <soc/northbridge.h>
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#include <soc/systemagent.h>
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#include <soc/pci_devs.h>
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#include <soc/pm.h>
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#include <soc/uart.h>
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@ -51,16 +52,9 @@ static void enable_cmos_upper_bank(void)
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asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
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{
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device_t dev = SA_DEV_ROOT;
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device_t dev;
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/* Set PCI Express BAR */
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pci_io_write_config32(dev, PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS | 1);
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/*
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* Clear TSEG register - TSEG register comes out of reset with a
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* non-zero default value. Clear this register to ensure that there are
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* no surprises in CBMEM handling.
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*/
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pci_write_config32(dev, TSEG, 0);
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bootblock_systemagent_early_init();
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dev = PCH_DEV_P2SB;
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/* BAR and MMIO enable for IOSF, so that GPIOs can be configured */
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@ -37,7 +37,7 @@
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#include <spi-generic.h>
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#include <soc/pm.h>
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#include <soc/p2sb.h>
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#include <soc/northbridge.h>
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#include <soc/systemagent.h>
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#include "chip.h"
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@ -15,18 +15,10 @@
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* GNU General Public License for more details.
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*/
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#ifndef _SOC_APOLLOLAKE_NORTHBRIDGE_H_
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#define _SOC_APOLLOLAKE_NORTHBRIDGE_H_
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#ifndef SOC_APOLLOLAKE_SYSTEMAGENT_H
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#define SOC_APOLLOLAKE_SYSTEMAGENT_H
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#define MCHBAR 0x48
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#define PCIEXBAR 0x60
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#define PCIEX_SIZE (256 * MiB)
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#define BDSM 0xb0 /* Base Data Stolen Memory */
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#define BGSM 0xb4 /* Base GTT Stolen Memory */
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#define TSEG 0xb8 /* TSEG base */
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#define TOLUD 0xbc /* Top of Low Used Memory */
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#define TOUUD 0xa8 /* Top of Upper Usable DRAM */
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#include <intelblocks/systemagent.h>
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/* IMR registers are found under MCHBAR. */
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#define MCHBAR_IMR0BASE 0x6870
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@ -37,4 +29,4 @@
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/* RAPL Package Power Limit register under MCHBAR. */
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#define MCHBAR_RAPL_PPL 0x70A8
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#endif /* _SOC_APOLLOLAKE_NORTHBRIDGE_H_ */
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#endif /* SOC_APOLLOLAKE_SYSTEMAGENT_H */
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@ -27,7 +27,7 @@
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#include <assert.h>
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#include <cbmem.h>
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#include <device/pci.h>
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#include <soc/northbridge.h>
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#include <soc/systemagent.h>
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#include <soc/pci_devs.h>
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#include <soc/smm.h>
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@ -20,7 +20,7 @@
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#include <soc/iomap.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <soc/northbridge.h>
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#include <soc/systemagent.h>
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#include <soc/pci_ids.h>
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static uint32_t get_bar(device_t dev, unsigned int index)
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@ -39,7 +39,7 @@ static int mc_add_fixed_mmio_resources(device_t dev, int index)
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/* PCI extended config region */
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addr = ALIGN_DOWN(get_bar(dev, PCIEXBAR), 256*MiB) / KiB;
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mmio_resource(dev, index++, addr, PCIEX_SIZE / KiB);
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mmio_resource(dev, index++, addr, CONFIG_SA_PCIEX_LENGTH / KiB);
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/* Memory Controller Hub */
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addr = ALIGN_DOWN(get_bar(dev, MCHBAR), 32*KiB) / KiB;
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@ -35,7 +35,7 @@
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#include <soc/flash_ctrlr.h>
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#include <soc/intel/common/mrc_cache.h>
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#include <soc/iomap.h>
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#include <soc/northbridge.h>
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#include <soc/systemagent.h>
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#include <soc/pci_devs.h>
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#include <soc/pm.h>
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#include <soc/romstage.h>
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