soc/intel/apollolake: Clean up code by using common System Agent module

This patch currently contains the SA initialization
required for bootblock phase -

1. Use SOC_INTEL_COMMON_BLOCK_SA kconfig for common SA code.
2. Perform PCIEXBAR programming based on soc configurable
    PCIEX_LENGTH_xxxMB
3. Use common systemagent header file.

Change-Id: I01a24e2d4f1c8c9ca113c128bb6b3eac23dc79ad
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/18567
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)

src/soc/intel/apollolake/Kconfig

@@ -41,6 +41,7 @@ config CPU_SPECIFIC_OPTIONS
 	select PCIEXP_COMMON_CLOCK
 	select PCIEXP_CLK_PM
 	select PCIEXP_L1_SUB_STATE
+	select PCIEX_LENGTH_256MB
 	select POSTCAR_CONSOLE
 	select POSTCAR_STAGE
 	select REG_SCRIPT
@@ -51,6 +52,7 @@ config CPU_SPECIFIC_OPTIONS
 	select SOC_INTEL_COMMON_ACPI
 	select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
 	select SOC_INTEL_COMMON_BLOCK
+	select SOC_INTEL_COMMON_BLOCK_SA
 	select SOC_INTEL_COMMON_LPSS_I2C
 	select SOC_INTEL_COMMON_SMI
 	select SOC_INTEL_COMMON_SPI_FLASH_PROTECT
@@ -89,10 +91,6 @@ config SOC_INTEL_COMMON_RESET
 	bool
 	default y
 
-config MMCONF_BASE_ADDRESS
-	hex "PCI MMIO Base Address"
-	default 0xe0000000
-
 config IOSF_BASE_ADDRESS
 	hex "MMIO Base Address of sideband bus"
 	default 0xd0000000
@@ -283,7 +281,7 @@ config USE_APOLLOLAKE_FSP_CAR
 	bool "Use FSP CAR"
 	select FSP_CAR
 	help
-	  Use FSP APIs to initialize & tear Down the Cache-As-Ram.
+	  Use FSP APIs to initialize & tear down the Cache-As-Ram.
 
 endchoice
 

src/soc/intel/apollolake/bootblock/bootblock.c

@@ -18,6 +18,7 @@
 #include <bootblock_common.h>
 #include <cpu/x86/mtrr.h>
 #include <device/pci.h>
+#include <intelblocks/systemagent.h>
 #include <lib.h>
 #include <soc/iomap.h>
 #include <soc/cpu.h>
@@ -25,7 +26,7 @@
 #include <soc/gpio.h>
 #include <soc/iosf.h>
 #include <soc/mmap_boot.h>
-#include <soc/northbridge.h>
+#include <soc/systemagent.h>
 #include <soc/pci_devs.h>
 #include <soc/pm.h>
 #include <soc/uart.h>
@@ -51,16 +52,9 @@ static void enable_cmos_upper_bank(void)
 
 asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
 {
-	device_t dev = SA_DEV_ROOT;
+	device_t dev;
 
-	/* Set PCI Express BAR */
+	bootblock_systemagent_early_init();
-	pci_io_write_config32(dev, PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS | 1);
-	/*
-	 * Clear TSEG register - TSEG register comes out of reset with a
-	 * non-zero default value. Clear this register to ensure that there are
-	 * no surprises in CBMEM handling.
-	 */
-	pci_write_config32(dev, TSEG, 0);
 
 	dev = PCH_DEV_P2SB;
 	/* BAR and MMIO enable for IOSF, so that GPIOs can be configured */

src/soc/intel/apollolake/chip.c

@@ -37,7 +37,7 @@
 #include <spi-generic.h>
 #include <soc/pm.h>
 #include <soc/p2sb.h>
-#include <soc/northbridge.h>
+#include <soc/systemagent.h>
 
 #include "chip.h"
 

src/soc/intel/apollolake/include/soc/systemagent.h

@@ -15,18 +15,10 @@
  * GNU General Public License for more details.
  */
 
-#ifndef _SOC_APOLLOLAKE_NORTHBRIDGE_H_
+#ifndef SOC_APOLLOLAKE_SYSTEMAGENT_H
-#define _SOC_APOLLOLAKE_NORTHBRIDGE_H_
+#define SOC_APOLLOLAKE_SYSTEMAGENT_H
 
-#define MCHBAR		0x48
+#include <intelblocks/systemagent.h>
-#define PCIEXBAR	0x60
-#define PCIEX_SIZE	(256 * MiB)
-
-#define BDSM		0xb0	/* Base Data Stolen Memory */
-#define BGSM		0xb4	/* Base GTT Stolen Memory */
-#define TSEG		0xb8	/* TSEG base */
-#define TOLUD		0xbc	/* Top of Low Used Memory */
-#define TOUUD		0xa8	/* Top of Upper Usable DRAM */
 
 /* IMR registers are found under MCHBAR. */
 #define MCHBAR_IMR0BASE		0x6870
@@ -37,4 +29,4 @@
 /* RAPL Package Power Limit register under MCHBAR. */
 #define MCHBAR_RAPL_PPL		0x70A8
 
-#endif /* _SOC_APOLLOLAKE_NORTHBRIDGE_H_ */
+#endif /* SOC_APOLLOLAKE_SYSTEMAGENT_H */

src/soc/intel/apollolake/memmap.c

@@ -27,7 +27,7 @@
 #include <assert.h>
 #include <cbmem.h>
 #include <device/pci.h>
-#include <soc/northbridge.h>
+#include <soc/systemagent.h>
 #include <soc/pci_devs.h>
 #include <soc/smm.h>
 

src/soc/intel/apollolake/northbridge.c

@@ -20,7 +20,7 @@
 #include <soc/iomap.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
-#include <soc/northbridge.h>
+#include <soc/systemagent.h>
 #include <soc/pci_ids.h>
 
 static uint32_t get_bar(device_t dev, unsigned int index)
@@ -39,7 +39,7 @@ static int mc_add_fixed_mmio_resources(device_t dev, int index)
 
 	/* PCI extended config region */
 	addr = ALIGN_DOWN(get_bar(dev, PCIEXBAR), 256*MiB) / KiB;
-	mmio_resource(dev, index++, addr, PCIEX_SIZE / KiB);
+	mmio_resource(dev, index++, addr, CONFIG_SA_PCIEX_LENGTH / KiB);
 
 	/* Memory Controller Hub */
 	addr = ALIGN_DOWN(get_bar(dev, MCHBAR), 32*KiB) / KiB;

src/soc/intel/apollolake/romstage.c

@@ -35,7 +35,7 @@
 #include <soc/flash_ctrlr.h>
 #include <soc/intel/common/mrc_cache.h>
 #include <soc/iomap.h>
-#include <soc/northbridge.h>
+#include <soc/systemagent.h>
 #include <soc/pci_devs.h>
 #include <soc/pm.h>
 #include <soc/romstage.h>