soc/amd/cezanne: Port ACPI p-state and c-state entries from picasso
Add generate_cpu_entries to device operations. Add support to generate cpu p-state and c-state SSDT entries. BUG=b:184151560 TEST=Dump and verify SSDT entry for CPU p-states and c-states. Change-Id: I77d8078b94fb661dc045b4184955c8cbec373d12 Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Signed-off-by: Mathew King <mathewk@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52036 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This commit is contained in:
Jason Glenesk
Patrick Georgi
parent
40df8aa84b
commit
79542fa36f
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@ -216,6 +216,14 @@ config DISABLE_KEYBOARD_RESET_PIN
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functionality isn't disabled, configuring it as an output and driving
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it as 0 will cause a reset.
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config ACPI_SSDT_PSD_INDEPENDENT
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bool "Allow core p-state independent transitions"
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default y
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help
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AMD recommends the ACPI _PSD object to be configured to cause
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cores to transition between p-states independently. A vendor may
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choose to generate _PSD object to allow cores to transition together.
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menu "PSP Configuration Options"
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config AMD_FWM_POSITION_INDEX
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@ -3,15 +3,20 @@
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/* ACPI - create the Fixed ACPI Description Tables (FADT) */
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#include <acpi/acpi.h>
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#include <acpi/acpigen.h>
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#include <amdblocks/acpi.h>
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#include <amdblocks/cpu.h>
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#include <amdblocks/acpimmio.h>
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#include <amdblocks/ioapic.h>
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#include <arch/ioapic.h>
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#include <arch/smp/mpspec.h>
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#include <console/console.h>
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#include <cpu/amd/cpuid.h>
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#include <cpu/amd/msr.h>
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#include <cpu/x86/smm.h>
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#include <soc/acpi.h>
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#include <soc/iomap.h>
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#include <soc/msr.h>
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#include <types.h>
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#include "chip.h"
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@ -121,3 +126,224 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
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fadt->x_gpe0_blk.addrl = ACPI_GPE0_BLK;
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fadt->x_gpe0_blk.addrh = 0x0;
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}
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static uint32_t get_pstate_core_freq(msr_t pstate_def)
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{
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uint32_t core_freq, core_freq_mul, core_freq_div;
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bool valid_freq_divisor;
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/* Core frequency multiplier */
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core_freq_mul = pstate_def.lo & PSTATE_DEF_LO_FREQ_MUL_MASK;
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/* Core frequency divisor ID */
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core_freq_div =
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(pstate_def.lo & PSTATE_DEF_LO_FREQ_DIV_MASK) >> PSTATE_DEF_LO_FREQ_DIV_SHIFT;
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if (core_freq_div == 0) {
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return 0;
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} else if ((core_freq_div >= PSTATE_DEF_LO_FREQ_DIV_MIN)
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&& (core_freq_div <= PSTATE_DEF_LO_EIGHTH_STEP_MAX)) {
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/* Allow 1/8 integer steps for this range */
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valid_freq_divisor = 1;
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} else if ((core_freq_div > PSTATE_DEF_LO_EIGHTH_STEP_MAX)
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&& (core_freq_div <= PSTATE_DEF_LO_FREQ_DIV_MAX) && !(core_freq_div & 0x1)) {
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/* Only allow 1/4 integer steps for this range */
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valid_freq_divisor = 1;
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} else {
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valid_freq_divisor = 0;
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}
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if (valid_freq_divisor) {
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/* 25 * core_freq_mul / (core_freq_div / 8) */
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core_freq =
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((PSTATE_DEF_LO_CORE_FREQ_BASE * core_freq_mul * 8) / (core_freq_div));
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} else {
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printk(BIOS_WARNING, "Undefined core_freq_div %x used. Force to 1.\n",
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core_freq_div);
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core_freq = (PSTATE_DEF_LO_CORE_FREQ_BASE * core_freq_mul);
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}
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return core_freq;
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}
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static uint32_t get_pstate_core_power(msr_t pstate_def)
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{
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uint32_t voltage_in_uvolts, core_vid, current_value_amps, current_divisor, power_in_mw;
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/* Core voltage ID */
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core_vid =
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(pstate_def.lo & PSTATE_DEF_LO_CORE_VID_MASK) >> PSTATE_DEF_LO_CORE_VID_SHIFT;
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/* Current value in amps */
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current_value_amps =
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(pstate_def.lo & PSTATE_DEF_LO_CUR_VAL_MASK) >> PSTATE_DEF_LO_CUR_VAL_SHIFT;
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/* Current divisor */
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current_divisor =
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(pstate_def.lo & PSTATE_DEF_LO_CUR_DIV_MASK) >> PSTATE_DEF_LO_CUR_DIV_SHIFT;
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/* Voltage */
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if ((core_vid >= 0xF8) && (core_vid <= 0xFF)) {
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/* Voltage off for VID codes 0xF8 to 0xFF */
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voltage_in_uvolts = 0;
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} else {
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voltage_in_uvolts =
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SERIAL_VID_MAX_MICROVOLTS - (SERIAL_VID_DECODE_MICROVOLTS * core_vid);
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}
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/* Power in mW */
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power_in_mw = (voltage_in_uvolts) / 1000 * current_value_amps;
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switch (current_divisor) {
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case 0:
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break;
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case 1:
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power_in_mw = power_in_mw / 10L;
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break;
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case 2:
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power_in_mw = power_in_mw / 100L;
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break;
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case 3:
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/* current_divisor is set to an undefined value.*/
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printk(BIOS_WARNING, "Undefined current_divisor set for enabled P-state .\n");
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power_in_mw = 0;
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break;
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}
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return power_in_mw;
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}
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/*
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* Populate structure describing enabled p-states and return count of enabled p-states.
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*/
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static size_t get_pstate_info(struct acpi_sw_pstate *pstate_values,
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struct acpi_xpss_sw_pstate *pstate_xpss_values)
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{
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msr_t pstate_def;
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size_t pstate_count, pstate;
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uint32_t pstate_enable, max_pstate;
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pstate_count = 0;
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max_pstate = (rdmsr(PS_LIM_REG).lo & PS_LIM_MAX_VAL_MASK) >> PS_MAX_VAL_SHFT;
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for (pstate = 0; pstate <= max_pstate; pstate++) {
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pstate_def = rdmsr(PSTATE_0_MSR + pstate);
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pstate_enable = (pstate_def.hi & PSTATE_DEF_HI_ENABLE_MASK)
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>> PSTATE_DEF_HI_ENABLE_SHIFT;
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if (!pstate_enable)
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continue;
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pstate_values[pstate_count].core_freq = get_pstate_core_freq(pstate_def);
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pstate_values[pstate_count].power = get_pstate_core_power(pstate_def);
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pstate_values[pstate_count].transition_latency = 0;
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pstate_values[pstate_count].bus_master_latency = 0;
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pstate_values[pstate_count].control_value = pstate;
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pstate_values[pstate_count].status_value = pstate;
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pstate_xpss_values[pstate_count].core_freq =
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(uint64_t)pstate_values[pstate_count].core_freq;
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pstate_xpss_values[pstate_count].power =
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(uint64_t)pstate_values[pstate_count].power;
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pstate_xpss_values[pstate_count].transition_latency = 0;
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pstate_xpss_values[pstate_count].bus_master_latency = 0;
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pstate_xpss_values[pstate_count].control_value = (uint64_t)pstate;
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pstate_xpss_values[pstate_count].status_value = (uint64_t)pstate;
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pstate_count++;
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}
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return pstate_count;
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}
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void generate_cpu_entries(const struct device *device)
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{
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int logical_cores;
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size_t pstate_count, cpu, proc_blk_len;
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struct acpi_sw_pstate pstate_values[MAX_PSTATES] = { {0} };
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struct acpi_xpss_sw_pstate pstate_xpss_values[MAX_PSTATES] = { {0} };
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uint32_t threads_per_core, proc_blk_addr;
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uint32_t cstate_base_address =
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rdmsr(MSR_CSTATE_ADDRESS).lo & MSR_CSTATE_ADDRESS_MASK;
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const acpi_addr_t perf_ctrl = {
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.space_id = ACPI_ADDRESS_SPACE_FIXED,
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.bit_width = 64,
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.addrl = PS_CTL_REG,
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};
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const acpi_addr_t perf_sts = {
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.space_id = ACPI_ADDRESS_SPACE_FIXED,
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.bit_width = 64,
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.addrl = PS_STS_REG,
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};
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acpi_cstate_t cstate_info[] = {
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[0] = {
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.ctype = 1,
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.latency = 1,
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.power = 0,
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.resource = {
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.space_id = ACPI_ADDRESS_SPACE_FIXED,
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.bit_width = 2,
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.bit_offset = 2,
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.addrl = 0,
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.addrh = 0,
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},
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},
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[1] = {
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.ctype = 2,
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.latency = 0x12,
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.power = 0,
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.resource = {
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.space_id = ACPI_ADDRESS_SPACE_IO,
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.bit_width = 8,
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.bit_offset = 0,
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.addrl = cstate_base_address + 1,
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.addrh = 0,
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.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS,
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},
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},
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};
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threads_per_core = ((cpuid_ebx(CPUID_EBX_CORE_ID) & CPUID_EBX_THREADS_MASK)
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>> CPUID_EBX_THREADS_SHIFT)
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+ 1;
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pstate_count = get_pstate_info(pstate_values, pstate_xpss_values);
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logical_cores = get_cpu_count();
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for (cpu = 0; cpu < logical_cores; cpu++) {
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if (cpu == 0) {
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/* BSP values for \_SB.Pxxx */
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proc_blk_len = 6;
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proc_blk_addr = ACPI_GPE0_BLK;
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} else {
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/* AP values for \_SB.Pxxx */
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proc_blk_addr = 0;
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proc_blk_len = 0;
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}
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acpigen_write_processor(cpu, proc_blk_addr, proc_blk_len);
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acpigen_write_pct_package(&perf_ctrl, &perf_sts);
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acpigen_write_pss_object(pstate_values, pstate_count);
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acpigen_write_xpss_object(pstate_xpss_values, pstate_count);
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if (CONFIG(ACPI_SSDT_PSD_INDEPENDENT))
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acpigen_write_PSD_package(cpu / threads_per_core, threads_per_core,
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HW_ALL);
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else
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acpigen_write_PSD_package(0, logical_cores, SW_ALL);
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acpigen_write_PPC(0);
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acpigen_write_CST_package(cstate_info, ARRAY_SIZE(cstate_info));
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acpigen_write_CSD_package(cpu / threads_per_core, threads_per_core,
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CSD_HW_ALL, 0);
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acpigen_pop_len();
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}
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acpigen_write_processor_package("PPKG", 0, logical_cores);
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}
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@ -4,6 +4,7 @@
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#include <device/device.h>
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#include <device/pci.h>
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#include <fsp/api.h>
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#include <soc/cpu.h>
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#include <soc/data_fabric.h>
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#include <soc/pci_devs.h>
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#include <soc/southbridge.h>
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@ -19,6 +20,7 @@ struct device_operations cpu_bus_ops = {
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.read_resources = noop_read_resources,
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.set_resources = noop_set_resources,
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.init = mp_cpu_bus_init,
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.acpi_fill_ssdt = generate_cpu_entries,
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};
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static const char *soc_acpi_name(const struct device *dev)
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