GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

soc/amd/stoneyridge: Use common prepare_and_run_postcar 

This reduces boilerplate postcar frame setup.

Change-Id: I8e258113c90ee49864ceddf36ea296ba6f83afe4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61961
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This commit is contained in:
Arthur Heymans 2022-02-15 10:59:41 +01:00
parent 46b409da48
commit 796147f5ca
1 changed files with 8 additions and 20 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

28
src/soc/amd/stoneyridge/romstage.c
View File

@ -23,6 +23,7 @@
#include <soc/pci_devs.h> #include <soc/pci_devs.h>
#include <soc/southbridge.h> #include <soc/southbridge.h>
#include <amdblocks/psp.h> #include <amdblocks/psp.h>
#include <stdint.h>
#include "chip.h" #include "chip.h"
@ -50,7 +51,6 @@ static void bsp_agesa_call(void)
asmlinkage void car_stage_entry(void) asmlinkage void car_stage_entry(void)
{ {
struct postcar_frame pcf; struct postcar_frame pcf;
uintptr_t top_of_ram;
msr_t base, mask; msr_t base, mask;
msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR); msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR);
int vmtrrs = mtrr_cap.lo & MTRR_CAP_VCNT; int vmtrrs = mtrr_cap.lo & MTRR_CAP_VCNT;
@ -121,28 +121,16 @@ asmlinkage void car_stage_entry(void)
smm_list_regions(); smm_list_regions();
post_code(0x44); post_code(0x44);
if (postcar_frame_init(&pcf)) prepare_and_run_postcar(&pcf);
die("Unable to initialize postcar frame.\n"); }
/* void fill_postcar_frame(struct postcar_frame *pcf)
* We need to make sure ramstage will be run cached. At this point exact {
* location of ramstage in cbmem is not known. Instruct postcar to cache uintptr_t top_of_ram = (uintptr_t)cbmem_top();
* 16 megs under cbmem top which is a safe bet to cover ramstage. postcar_frame_add_mtrr(pcf, top_of_ram - 16 * MiB, 16 * MiB, MTRR_TYPE_WRBACK);
*/
top_of_ram = (uintptr_t) cbmem_top();
postcar_frame_add_mtrr(&pcf, top_of_ram - 16*MiB, 16*MiB,
MTRR_TYPE_WRBACK);
/* Cache the memory-mapped boot media. */
postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT);
/* Cache the TSEG region */ /* Cache the TSEG region */
postcar_enable_tseg_cache(&pcf); postcar_enable_tseg_cache(pcf);
post_code(0x45);
run_postcar_phase(&pcf);
post_code(0x50); /* Should never see this post code. */
} }
void SetMemParams(AMD_POST_PARAMS *PostParams) void SetMemParams(AMD_POST_PARAMS *PostParams)