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mb/google/poppy: Configure WWAN gpios 

BUG=b:70773281

Change-Id: If9b575568cabcbee03ad190b69d9c033890f7fa6
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22927
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Furquan Shaikh 2017-12-17 21:58:55 -08:00 committed by Furquan Shaikh
parent 5e9ba6e3b4
commit 796abaeeb6
1 changed files with 8 additions and 8 deletions
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16
src/mainboard/google/poppy/variants/baseboard/gpio.c
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@ -160,16 +160,16 @@ static const struct pad_config gpio_table[] = {
/* C23 : UART2_CTS# ==> PCH_WP */ /* C23 : UART2_CTS# ==> PCH_WP */
PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP),
/* D0 : SPI1_CS# ==> NC */ /* D0 : SPI1_CS# ==> EN_PP3300_DX_LTE */
PAD_CFG_NC(GPP_D0), PAD_CFG_GPO(GPP_D0, 1, DEEP),
/* D1 : SPI1_CLK ==> PEN_IRQ_L */ /* D1 : SPI1_CLK ==> PEN_IRQ_L */
PAD_CFG_GPI_APIC(GPP_D1, NONE, PLTRST), PAD_CFG_GPI_APIC(GPP_D1, NONE, PLTRST),
/* D2 : SPI1_MISO ==> PEN_PDCT_L */ /* D2 : SPI1_MISO ==> PEN_PDCT_L */
PAD_CFG_GPI_GPIO_DRIVER(GPP_D2, NONE, DEEP), PAD_CFG_GPI_GPIO_DRIVER(GPP_D2, NONE, DEEP),
/* D3 : SPI1_MOSI ==> PEN_RST_L */ /* D3 : SPI1_MOSI ==> PEN_RST_L */
PAD_CFG_GPO(GPP_D3, 0, DEEP), PAD_CFG_GPO(GPP_D3, 0, DEEP),
/* D4 : FASHTRIG ==> NC */ /* D4 : FASHTRIG ==> LTE_GPS_OFF_ODL */
PAD_CFG_NC(GPP_D4), PAD_CFG_GPO(GPP_D4, 1, DEEP),
/* D5 : ISH_I2C0_SDA ==> ISH_I2C_SENSOR_1V8_SDA */ /* D5 : ISH_I2C0_SDA ==> ISH_I2C_SENSOR_1V8_SDA */
PAD_CFG_NF_1V8(GPP_D5, NONE, DEEP, NF1), PAD_CFG_NF_1V8(GPP_D5, NONE, DEEP, NF1),
/* D6 : ISH_I2C0_SCL ==> ISH_I2C_SENSOR_1V8_SCL */ /* D6 : ISH_I2C0_SCL ==> ISH_I2C_SENSOR_1V8_SCL */
@ -192,8 +192,8 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_NC(GPP_D14), PAD_CFG_NC(GPP_D14),
/* D15 : ISH_UART0_RTS# ==> NC */ /* D15 : ISH_UART0_RTS# ==> NC */
PAD_CFG_NC(GPP_D15), PAD_CFG_NC(GPP_D15),
/* D16 : ISH_UART0_CTS# ==> NC */ /* D16 : ISH_UART0_CTS# ==> LTE_OFF_ODL */
PAD_CFG_NC(GPP_D16), PAD_CFG_GPO(GPP_D16, 1, DEEP),
/* D17 : DMIC_CLK1 */ /* D17 : DMIC_CLK1 */
PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
/* D18 : DMIC_DATA1 */ /* D18 : DMIC_DATA1 */
@ -202,8 +202,8 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
/* D20 : DMIC_DATA0 */ /* D20 : DMIC_DATA0 */
PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
/* D21 : SPI1_IO2 ==> NC */ /* D21 : SPI1_IO2 ==> LTE_BODY_SAR_ODL */
PAD_CFG_NC(GPP_D21), PAD_CFG_GPO(GPP_D21, 1, DEEP),
/* D22 : SPI1_IO3 ==> BOOT_BEEP_OVERRIDE */ /* D22 : SPI1_IO3 ==> BOOT_BEEP_OVERRIDE */
PAD_CFG_GPO(GPP_D22, 1, DEEP), PAD_CFG_GPO(GPP_D22, 1, DEEP),
/* D23 : I2S_MCLK ==> I2S_MCLK_R */ /* D23 : I2S_MCLK ==> I2S_MCLK_R */