src/mb/apple/macbookair4_2: move early_southbridge.c to romstage.c
This is done for consistency purposes. Also fix a small formatting issue in a function. Change-Id: I5dc170dbca59b7abbc912f9a26f76886b25ad82f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/30654 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Angel Pons
Nico Huber
parent
63649d24fd
commit
796bd74d63
3 changed files with 77 additions and 79 deletions
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@ -1,4 +1,3 @@
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romstage-y += early_southbridge.c
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romstage-y += gpio.c
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ramstage-y += gnvs.c
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@ -1,76 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <stdint.h>
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#include <string.h>
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#include <arch/byteorder.h>
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#include <arch/io.h>
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#include <device/pci_def.h>
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#include <device/pnp_def.h>
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#include <northbridge/intel/sandybridge/sandybridge.h>
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#include <northbridge/intel/sandybridge/raminit_native.h>
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#include <southbridge/intel/bd82x6x/pch.h>
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#include <cbfs.h>
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void pch_enable_lpc(void)
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{
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pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0f);
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pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x000c0681);
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pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000c1641);
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pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x001c0301);
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pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00fc0701);
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pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0070);
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pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xac, 0x80000000);
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}
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void mainboard_rcba_config(void)
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{
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/* Disable devices. */
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RCBA32(0x3414) = 0x00000020;
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}
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const struct southbridge_usb_port mainboard_usb_ports[] = {
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{ 1, 0, -1 },
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{ 1, 0, -1 },
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{ 1, 0, -1 },
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{ 1, 0, -1 },
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{ 1, 0, -1 },
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{ 1, 0, -1 },
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{ 1, 0, -1 },
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{ 1, 0, -1 },
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{ 1, 0, -1 },
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{ 1, 0, -1 },
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{ 1, 0, -1 },
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{ 1, 0, -1 },
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{ 1, 0, -1 },
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{ 1, 0, -1 },
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};
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void mainboard_early_init(int s3resume) {
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}
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void mainboard_config_superio(void)
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{
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}
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void mainboard_get_spd(spd_raw_data *spd, bool id_only)
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{
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void *spd_file;
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size_t spd_file_len = 0;
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spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD,
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&spd_file_len);
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if (spd_file && spd_file_len >= 1024) {
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int i;
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for (i = 0; i < 4; i++)
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memcpy(&spd[i], spd_file + 256 * i, 128);
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}
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}
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@ -1,2 +1,77 @@
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/* No license required */
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/* dummy file */
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/*
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* This file is part of the coreboot project.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <stdint.h>
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#include <string.h>
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#include <arch/byteorder.h>
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#include <arch/io.h>
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#include <device/pci_def.h>
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#include <device/pnp_def.h>
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#include <northbridge/intel/sandybridge/sandybridge.h>
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#include <northbridge/intel/sandybridge/raminit_native.h>
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#include <southbridge/intel/bd82x6x/pch.h>
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#include <cbfs.h>
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void pch_enable_lpc(void)
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{
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pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0f);
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pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x000c0681);
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pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000c1641);
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pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x001c0301);
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pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00fc0701);
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pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0070);
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pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xac, 0x80000000);
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}
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void mainboard_rcba_config(void)
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{
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/* Disable devices. */
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RCBA32(0x3414) = 0x00000020;
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}
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const struct southbridge_usb_port mainboard_usb_ports[] = {
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{ 1, 0, -1 },
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{ 1, 0, -1 },
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{ 1, 0, -1 },
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{ 1, 0, -1 },
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{ 1, 0, -1 },
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{ 1, 0, -1 },
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{ 1, 0, -1 },
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{ 1, 0, -1 },
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{ 1, 0, -1 },
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{ 1, 0, -1 },
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{ 1, 0, -1 },
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{ 1, 0, -1 },
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{ 1, 0, -1 },
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{ 1, 0, -1 },
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};
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void mainboard_early_init(int s3resume)
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{
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}
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void mainboard_config_superio(void)
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{
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}
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void mainboard_get_spd(spd_raw_data *spd, bool id_only)
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{
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void *spd_file;
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size_t spd_file_len = 0;
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spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD,
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&spd_file_len);
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if (spd_file && spd_file_len >= 1024) {
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int i;
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for (i = 0; i < 4; i++)
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memcpy(&spd[i], spd_file + 256 * i, 128);
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}
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}
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