diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c
index 21efc37a53..197c58fce5 100644
--- a/src/northbridge/intel/i945/early_init.c
+++ b/src/northbridge/intel/i945/early_init.c
@@ -42,7 +42,7 @@ static void i945m_detect_chipset(void)
 		printk(BIOS_INFO, "Mobile Intel(R) 82945GM/GME Express");
 		break;
 	case 2:
-		printk(BIOS_INFO, "Mobile Intel(R) 82945GMS/GU Express");
+		printk(BIOS_INFO, "Mobile Intel(R) 82945GMS/GU/GSE Express");
 		break;
 	case 3:
 		printk(BIOS_INFO, "Mobile Intel(R) 82945PM Express");
@@ -91,6 +91,9 @@ static void i945m_detect_chipset(void)
 		printk(BIOS_INFO, "unknown max. RAM clock (%02x).", reg8);	/* Others reserved. */
 	}
 	printk(BIOS_DEBUG, "\n");
+#if defined(CONFIG_NORTHBRIDGE_INTEL_I945GC)
+	printk(BIOS_ERR, "coreboot is compiled for the wrong chipset.\n");
+#endif
 }
 
 static void i945_detect_chipset(void)
@@ -137,6 +140,9 @@ static void i945_detect_chipset(void)
 		printk(BIOS_INFO, "unknown max. RAM clock (%02x).", reg8);	/* Others reserved. */
 	}
 	printk(BIOS_DEBUG, "\n");
+#if defined(CONFIG_NORTHBRIDGE_INTEL_I945GM)
+	printk(BIOS_ERR, "coreboot is compiled for the wrong chipset.\n");
+#endif
 }
 
 static void i945_setup_bars(void)