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This drops the ASSEMBLY define from romstage.c, too 

(since it's not assembly code, this was a dirty hack anyways)
Also run 
    awk 1 RS= ORS="\n\n" < $FILE > $FILE.nonewlines
    mv $FILE.nonewlines $FILE
on romstage.c because my perl -pi -e 's,#define ASSEMBLY 1,,g' */*/romstage.c 
cut some holes into the source.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5320 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer 2010-03-29 22:08:01 +00:00 committed by Stefan Reinauer
parent 72bdfeb698
commit 798ef2893c
123 changed files with 105 additions and 482 deletions
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4
src/mainboard/a-trend/atc-6220/romstage.c
View File

@ -18,9 +18,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define ASSEMBLY 1
#include <stdint.h>
#include <device/pci_def.h>
#include <arch/io.h>
@ -71,3 +68,4 @@ static void main(unsigned long bist)
sdram_enable();
/* ram_check(0, 640 * 1024); */
}

4
src/mainboard/a-trend/atc-6240/romstage.c
View File

@ -18,9 +18,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define ASSEMBLY 1
#include <stdint.h>
#include <stdlib.h>
#include <device/pci_def.h>
@ -71,3 +68,4 @@ static void main(unsigned long bist)
sdram_enable();
/* ram_check(0, 640 * 1024); */
}

4
src/mainboard/abit/be6-ii_v2_0/romstage.c
View File

@ -18,9 +18,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define ASSEMBLY 1
#include <stdint.h>
#include <stdlib.h>
#include <device/pci_def.h>
@ -74,3 +71,4 @@ static void main(unsigned long bist)
sdram_enable();
/* ram_check(0, 640 * 1024); */
}

4
src/mainboard/advantech/pcm-5820/romstage.c
View File

@ -18,9 +18,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define ASSEMBLY 1
#include <stdint.h>
#include <arch/io.h>
#include <device/pnp_def.h>
@ -46,3 +43,4 @@ static void main(unsigned long bist)
sdram_init();
/* ram_check(0, 640 * 1024); */
}

5
src/mainboard/amd/db800/romstage.c
View File

@ -18,9 +18,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define ASSEMBLY 1
#include <stdint.h>
#include <device/pci_def.h>
#include <arch/io.h>
@ -87,7 +84,6 @@ static const struct msrinit msr_table[] =
{MSR_GLIU1_SHADOW, {.hi = 0x2000FFFF,.lo = 0xFFFF0003}}, // 0xC0000-0xFFFFF
};
static void msr_init(void)
{
int i;
@ -133,3 +129,4 @@ void cache_as_ram_main(void)
/* Memory is setup. Return to cache_as_ram.inc and continue to boot. */
return;
}

5
src/mainboard/amd/dbm690t/romstage.c
View File

@ -17,9 +17,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define ASSEMBLY 1
#define RAMINIT_SYSINFO 1
#define K8_SET_FIDVID 1
#define QRANK_DIMM_SUPPORT 1
@ -179,7 +176,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
rs690_htinit();
printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset);
if (needs_reset) {
print_info("ht reset -\r\n");
soft_reset();
@ -198,3 +194,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_cache_as_ram();
}

4
src/mainboard/amd/mahogany/romstage.c
View File

@ -17,9 +17,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define ASSEMBLY 1
#define RAMINIT_SYSINFO 1
#define K8_SET_FIDVID 1
#define QRANK_DIMM_SUPPORT 1
@ -196,3 +193,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_cache_as_ram();
}

12
src/mainboard/amd/mahogany_fam10/romstage.c
View File

@ -17,15 +17,10 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define ASSEMBLY 1
//#define SYSTEM_TYPE 0 /* SERVER */
#define SYSTEM_TYPE 1 /* DESKTOP */
//#define SYSTEM_TYPE 2 /* MOBILE */
#define RAMINIT_SYSINFO 1
#define CACHE_AS_RAM_ADDRESS_DEBUG 1
@ -71,7 +66,6 @@ int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf,
#define printk(BIOS_INFO, fmt, arg...) do_printk(BIOS_INFO ,fmt, ##arg)
#include "cpu/x86/bist.h"
static int smbus_read_byte(u32 device, u32 address);
#include "superio/ite/it8718f/it8718f_early_serial.c"
@ -86,17 +80,14 @@ static void memreset_setup(void)
{
}
static void memreset(int controllers, const struct mem_controller *ctrl)
{
}
static void activate_spd_rom(const struct mem_controller *ctrl)
{
}
static int spd_read_byte(u32 device, u32 address)
{
int result;
@ -118,7 +109,6 @@ static int spd_read_byte(u32 device, u32 address)
#include "cpu/amd/model_10xxx/init_cpus.c"
#include "cpu/amd/model_10xxx/fidvid.c"
#include "northbridge/amd/amdfam10/early_ht.c"
#include "southbridge/amd/sb700/sb700_early_setup.c"
@ -281,7 +271,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// ram_check(0x00200000, 0x00200000 + (640 * 1024));
// ram_check(0x40200000, 0x40200000 + (640 * 1024));
// die("After MCT init before CAR disabled.");
rs780_before_pci_init();
@ -292,3 +281,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
post_code(0x43); // Should never see this post code.
}

3
src/mainboard/amd/norwich/romstage.c
View File

@ -18,8 +18,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define ASSEMBLY 1
#include <stdint.h>
#include <device/pci_def.h>
#include <arch/io.h>
@ -132,3 +130,4 @@ void cache_as_ram_main(void)
/* Memory is setup. Return to cache_as_ram.inc and continue to boot. */
return;
}

4
src/mainboard/amd/pistachio/romstage.c
View File

@ -17,9 +17,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define ASSEMBLY 1
#define RAMINIT_SYSINFO 1
#define K8_SET_FIDVID 1
#define QRANK_DIMM_SUPPORT 1
@ -208,3 +205,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_cache_as_ram();
}

5
src/mainboard/amd/rumba/romstage.c
View File

@ -1,6 +1,3 @@
#define ASSEMBLY 1
#include <stdint.h>
#include <device/pci_def.h>
#include <arch/io.h>
@ -118,7 +115,6 @@ static void msr_init(void)
/* put code in northbridge[init].c here */
}
static void main(unsigned long bist)
{
static const struct mem_controller memctrl [] = {
@ -146,3 +142,4 @@ static void main(unsigned long bist)
/* Check all of memory */
//ram_check(0x00000000, 640*1024);
}

8
src/mainboard/amd/serengeti_cheetah/romstage.c
View File

@ -1,6 +1,3 @@
#define ASSEMBLY 1
#define RAMINIT_SYSINFO 1
#define CACHE_AS_RAM_ADDRESS_DEBUG 0
@ -32,7 +29,6 @@
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#if 0
static void post_code(uint8_t value) {
#if 1
@ -50,8 +46,6 @@ static void post_code(uint8_t value) {
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
@ -142,7 +136,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#define DIMM6 0x56
#define DIMM7 0x57
#include "cpu/amd/car/copy_and_run.c"
#include "cpu/amd/car/post_cache_as_ram.c"
@ -330,3 +323,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
}

17
src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
View File

@ -17,15 +17,10 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define ASSEMBLY 1
#define SYSTEM_TYPE 0 /* SERVER */
//#define SYSTEM_TYPE 1 /* DESKTOP */
//#define SYSTEM_TYPE 2 /* MOBILE */
#define RAMINIT_SYSINFO 1
#define CACHE_AS_RAM_ADDRESS_DEBUG 1
@ -71,7 +66,6 @@ int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf,
#endif
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdfam10/debug.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
#include "cpu/amd/mtrr/amd_earlymtrr.c"
@ -87,12 +81,10 @@ static void memreset_setup(void)
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
}
static void memreset(int controllers, const struct mem_controller *ctrl)
{
}
static void activate_spd_rom(const struct mem_controller *ctrl)
{
#define SMBUS_HUB 0x18
@ -109,7 +101,6 @@ static void activate_spd_rom(const struct mem_controller *ctrl)
smbus_write_byte(SMBUS_HUB, 0x03, 0);
}
static int spd_read_byte(u32 device, u32 address)
{
int result;
@ -131,7 +122,6 @@ static int spd_read_byte(u32 device, u32 address)
#include "cpu/amd/model_10xxx/init_cpus.c"
#include "cpu/amd/model_10xxx/fidvid.c"
#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
#include "northbridge/amd/amdfam10/early_ht.c"
@ -244,7 +234,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
#endif
/* Reset for HT, FIDVID, PLL and errata changes to take affect. */
if (!warm_reset_detect(0)) {
print_info("...WARM RESET...\n\n\n");
@ -254,7 +243,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x3B);
/* FIXME: Move this to chipset init.
enable cf9 for hard reset */
print_debug("enable_cf9_x()\n");
@ -266,12 +254,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
post_code(0x3D);
printk(BIOS_DEBUG, "enable_smbus()\n");
enable_smbus();
post_code(0x3E);
memreset_setup();
post_code(0x40);
@ -281,7 +267,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
raminit_amdmct(sysinfo);
post_code(0x41);
/*
dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200);
dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200);
@ -292,7 +277,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// ram_check(0x00200000, 0x00200000 + (640 * 1024));
// ram_check(0x40200000, 0x40200000 + (640 * 1024));
// die("After MCT init before CAR disabled.");
post_code(0x42);
@ -300,6 +284,5 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
post_code(0x43); // Should never see this post code.
}

4
src/mainboard/arima/hdama/romstage.c
View File

@ -1,6 +1,3 @@
#define ASSEMBLY 1
#include <stdint.h>
#include <device/pci_def.h>
#include <arch/io.h>
@ -169,3 +166,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_cache_as_ram();
}

6
src/mainboard/artecgroup/dbe61/romstage.c
View File

@ -18,9 +18,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define ASSEMBLY 1
#include <stdint.h>
#include <device/pci_def.h>
#include <arch/io.h>
@ -38,7 +35,6 @@
#include "southbridge/amd/cs5536/cs5536.h"
#include "spd_table.h"
#define POST_CODE(x) outb(x, 0x80)
#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
@ -47,7 +43,6 @@
#define DIMM0 0xA0
#define DIMM1 0xA2
static int spd_read_byte(unsigned device, unsigned address)
{
int i;
@ -182,3 +177,4 @@ void cache_as_ram_main(void)
/* Memory is setup. Return to cache_as_ram.inc and continue to boot */
return;
}

4
src/mainboard/asi/mb_5blgp/romstage.c
View File

@ -18,9 +18,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define ASSEMBLY 1
#include <stdint.h>
#include <arch/io.h>
#include <device/pnp_def.h>
@ -46,3 +43,4 @@ static void main(unsigned long bist)
sdram_init();
/* ram_check(0, 640 * 1024); */
}

4
src/mainboard/asi/mb_5blmp/romstage.c
View File

@ -18,9 +18,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define ASSEMBLY 1
#include <stdint.h>
#include <device/pci_def.h>
#include <arch/io.h>
@ -55,3 +52,4 @@ static void main(unsigned long bist)
/* Check whether RAM works. */
/* ram_check(0x00000000, 0x4000); */
}

4
src/mainboard/asus/a8n_e/romstage.c
View File

@ -21,9 +21,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define ASSEMBLY 1
/* Used by it8712f_enable_serial(). */
#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
@ -195,3 +192,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_cache_as_ram();
}

4
src/mainboard/asus/a8v-e_se/romstage.c
View File

@ -22,9 +22,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define ASSEMBLY 1
#define RAMINIT_SYSINFO 1
#define CACHE_AS_RAM_ADDRESS_DEBUG 0
@ -259,3 +256,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
post_cache_as_ram();
}

8
src/mainboard/asus/m2v-mx_se/romstage.c
View File

@ -22,9 +22,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define ASSEMBLY 1
#define RAMINIT_SYSINFO 1
#define CACHE_AS_RAM_ADDRESS_DEBUG 0
@ -92,7 +89,6 @@ void activate_spd_rom(const struct mem_controller *ctrl)
#define K8_4RANK_DIMM_SUPPORT 1
#include "southbridge/via/k8t890/k8t890_early_car.c"
#include "northbridge/amd/amdk8/amdk8.h"
#include "northbridge/amd/amdk8/raminit_f.c"
@ -117,7 +113,6 @@ static void ldtstop_sb(void)
print_debug("done\r\n");
}
#include "cpu/amd/model_fxx/fidvid.c"
#include "northbridge/amd/amdk8/resourcemap.c"
@ -195,7 +190,6 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
print_info("now booting... real_main\r\n");
if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
@ -234,7 +228,6 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
}
/* the HT settings needs to be OK, because link freq chnage may cause HT disconnect */
/* allow LDT STOP asserts */
vt8237_sb_enable_fid_vid();
@ -254,3 +247,4 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
post_cache_as_ram();
}

4
src/mainboard/asus/mew-am/romstage.c
View File

@ -18,9 +18,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define ASSEMBLY 1
#include <stdint.h>
#include <stdlib.h>
#include <device/pci_def.h>
@ -66,3 +63,4 @@ static void main(unsigned long bist)
sdram_enable();
/* ram_check(0, 640 * 1024); */
}

4
src/mainboard/asus/mew-vm/romstage.c
View File

@ -18,9 +18,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define ASSEMBLY 1
#include <stdint.h>
#include <device/pci_def.h>
#include <arch/io.h>
@ -68,3 +65,4 @@ static void main(unsigned long bist)
/* Check RAM. */
/* ram_check(0, 640 * 1024); */
}

4
src/mainboard/asus/p2b-d/romstage.c
View File

@ -18,9 +18,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define ASSEMBLY 1
#include <stdint.h>
#include <device/pci_def.h>
#include <arch/io.h>
@ -74,3 +71,4 @@ static void main(unsigned long bist)
sdram_enable();
/* ram_check(0, 640 * 1024); */
}

4
src/mainboard/asus/p2b-ds/romstage.c
View File

@ -18,9 +18,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define ASSEMBLY 1
#include <stdint.h>
#include <device/pci_def.h>
#include <arch/io.h>
@ -74,3 +71,4 @@ static void main(unsigned long bist)
sdram_enable();
/* ram_check(0, 640 * 1024); */
}

4
src/mainboard/asus/p2b-f/romstage.c
View File

@ -18,9 +18,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define ASSEMBLY 1
#include <stdint.h>
#include <device/pci_def.h>
#include <arch/io.h>
@ -74,3 +71,4 @@ static void main(unsigned long bist)
sdram_enable();
/* ram_check(0, 640 * 1024); */
}

4
src/mainboard/asus/p2b-ls/romstage.c
View File

@ -18,9 +18,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define ASSEMBLY 1
#include <stdint.h>
#include <device/pci_def.h>
#include <arch/io.h>
@ -73,3 +70,4 @@ static void main(unsigned long bist)
sdram_enable();
/* ram_check(0, 640 * 1024); */
}

4
src/mainboard/asus/p2b/romstage.c
View File

@ -18,9 +18,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define ASSEMBLY 1
#include <stdint.h>
#include <device/pci_def.h>
#include <arch/io.h>
@ -71,3 +68,4 @@ static void main(unsigned long bist)
sdram_enable();
/* ram_check(0, 640 * 1024); */
}

4
src/mainboard/asus/p3b-f/romstage.c
View File

@ -18,9 +18,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define ASSEMBLY 1
#include <stdint.h>
#include <device/pci_def.h>
#include <arch/io.h>
@ -74,3 +71,4 @@ static void main(unsigned long bist)
sdram_enable();
/* ram_check(0, 640 * 1024); */
}

4
src/mainboard/axus/tc320/romstage.c
View File

@ -18,9 +18,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define ASSEMBLY 1
#include <stdint.h>
#include <device/pci_def.h>
#include <arch/io.h>
@ -47,3 +44,4 @@ static void main(unsigned long bist)
sdram_init();
/* ram_check(0, 640 * 1024); */
}

4
src/mainboard/azza/pt-6ibd/romstage.c
View File

@ -18,9 +18,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define ASSEMBLY 1
#include <stdint.h>
#include <device/pci_def.h>
#include <arch/io.h>
@ -74,3 +71,4 @@ static void main(unsigned long bist)
sdram_enable();
/* ram_check(0, 640 * 1024); */
}

4
src/mainboard/bcom/winnet100/romstage.c
View File

@ -18,9 +18,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define ASSEMBLY 1
#include <stdint.h>
#include <device/pci_def.h>
#include <arch/io.h>
@ -55,3 +52,4 @@ static void main(unsigned long bist)
/* Check whether RAM works. */
/* ram_check(0, 640 * 1024); */
}

4
src/mainboard/bcom/winnetp680/romstage.c
View File

@ -19,9 +19,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define ASSEMBLY 1
#include <stdint.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
@ -126,3 +123,4 @@ static void main(unsigned long bist)
print_spew("Leaving romstage.c:main()\r\n");
}

4
src/mainboard/biostar/m6tba/romstage.c
View File

@ -18,9 +18,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define ASSEMBLY 1
#include <stdint.h>
#include <device/pci_def.h>
#include <arch/io.h>
@ -71,3 +68,4 @@ static void main(unsigned long bist)
sdram_enable();
/* ram_check(0, 640 * 1024); */
}

4
src/mainboard/broadcom/blast/romstage.c
View File

@ -1,6 +1,3 @@
#define ASSEMBLY 1
#define QRANK_DIMM_SUPPORT 1
#if CONFIG_LOGICAL_CPUS==1
@ -215,3 +212,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_cache_as_ram();
}

4
src/mainboard/compaq/deskpro_en_sff_p600/romstage.c
View File

@ -18,9 +18,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define ASSEMBLY 1
#include <stdint.h>
#include <device/pci_def.h>
#include <arch/io.h>
@ -74,3 +71,4 @@ static void main(unsigned long bist)
sdram_enable();
/* ram_check(0, 640 * 1024); */
}

7
src/mainboard/dell/s1850/romstage.c
View File

@ -1,5 +1,3 @@
#define ASSEMBLY 1
#include <stdint.h>
#include <device/pci_def.h>
#include <arch/io.h>
@ -25,7 +23,6 @@
#include "northbridge/intel/e7520/memory_initialized.c"
#include "cpu/x86/bist.h"
#define SIO_GPIO_BASE 0x680
#define SIO_XBUS_BASE 0x4880
@ -59,7 +56,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "northbridge/intel/e7520/raminit.c"
#include "lib/generic_sdram.c"
/* IPMI garbage. This is all test stuff, if it really works we'll move it somewhere
*/
@ -71,7 +67,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#define ipmidata 0xca0
#define ipmicsr 0xca4
static inline void ibfzero(void)
{
while(inb(ipmicsr) & (1<<IBF))
@ -290,7 +285,6 @@ static void main(unsigned long bist)
uart_init();
console_init();
/* stuff we seem to need */
pc8374_enable_dev(PNP_DEV(0x2e, PC8374_KBCK), 0);
@ -371,3 +365,4 @@ static void main(unsigned long bist)
}
#endif
}

7
src/mainboard/digitallogic/adl855pc/romstage.c
View File

@ -1,5 +1,3 @@
#define ASSEMBLY 1
#define ASM_CONSOLE_LOGLEVEL 8
#include <stdint.h>
#include <device/pci_def.h>
@ -46,8 +44,6 @@ static void memreset(int controllers, const struct mem_controller *ctrl)
{
}
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
/* nothing to do */
@ -83,7 +79,6 @@ static void main(unsigned long bist)
uart_init();
console_init();
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
@ -99,7 +94,6 @@ static void main(unsigned long bist)
// dump_smbus_registers();
#endif
memreset_setup();
sdram_initialize(ARRAY_SIZE(memctrl), memctrl);
@ -142,3 +136,4 @@ static void main(unsigned long bist)
#endif
*/
}

11
src/mainboard/digitallogic/msm586seg/romstage.c
View File

@ -1,5 +1,3 @@
#define ASSEMBLY 1
#define ASM_CONSOLE_LOGLEVEL 8
#include <stdint.h>
#include <device/pci_def.h>
@ -45,8 +43,6 @@ void setup_pars(void)
typedef void (*lj)(void);
struct mem_controller {
int i;
};
@ -59,8 +55,6 @@ static void memreset(int controllers, const struct mem_controller *ctrl)
{
}
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
/* nothing to do */
@ -90,7 +84,6 @@ static inline void dumpmem(void){
}
}
static inline void irqinit(void){
volatile unsigned char *cp;
#if 0
@ -186,15 +179,12 @@ static inline void irqinit(void){
#endif
}
static void main(unsigned long bist)
{
volatile int i;
for(i = 0; i < 100; i++)
;
setupsc520();
irqinit();
uart_init();
@ -213,7 +203,6 @@ static void main(unsigned long bist)
outb(0xee, 0x80);
print_err("loop forever ...\n");
#if 0
/* clear memory 1meg */

4
src/mainboard/digitallogic/msm800sev/romstage.c
View File

@ -1,6 +1,3 @@
#define ASSEMBLY 1
#include <stdint.h>
#include <device/pci_def.h>
#include <arch/io.h>
@ -118,3 +115,4 @@ void cache_as_ram_main(void)
void done_cache_as_ram_main(void);
done_cache_as_ram_main();
}

4
src/mainboard/eaglelion/5bcm/romstage.c
View File

@ -1,6 +1,3 @@
#define ASSEMBLY 1
#include <stdint.h>
#include <device/pci_def.h>
#include <arch/io.h>
@ -57,3 +54,4 @@ static void main(unsigned long bist)
}
#endif
}

3
src/mainboard/emulation/qemu-x86/romstage.c
View File

@ -1,5 +1,3 @@
#define ASSEMBLY 1
#include <stdint.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
@ -26,3 +24,4 @@ static void main(void)
//print_pci_devices();
//dump_pci_devices();
}

4
src/mainboard/gigabyte/ga-6bxc/romstage.c
View File

@ -18,9 +18,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define ASSEMBLY 1
#include <stdint.h>
#include <device/pci_def.h>
#include <arch/io.h>
@ -71,3 +68,4 @@ static void main(unsigned long bist)
sdram_enable();
/* ram_check(0, 640 * 1024); */
}

5
src/mainboard/gigabyte/ga_2761gxdk/romstage.c
View File

@ -21,9 +21,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define ASSEMBLY 1
#define RAMINIT_SYSINFO 1
#define K8_ALLOCATE_IO_RANGE 1
@ -147,7 +144,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "northbridge/amd/amdk8/early_ht.c"
static void sio_setup(void)
{
@ -212,7 +208,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
#if CONFIG_USBDEBUG_DIRECT
sis966_enable_usbdebug_direct(DBGP_DEFAULT);
early_usbdebug_direct_init();

6
src/mainboard/gigabyte/m57sli/romstage.c
View File

@ -19,9 +19,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define ASSEMBLY 1
#define RAMINIT_SYSINFO 1
#define K8_ALLOCATE_IO_RANGE 1
@ -146,7 +143,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
static void sio_setup(void)
{
@ -167,7 +163,6 @@ static void sio_setup(void)
pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword);
}
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr [] = {
@ -226,7 +221,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
#if CONFIG_USBDEBUG_DIRECT
mcp55_enable_usbdebug_direct(DBGP_DEFAULT);
early_usbdebug_direct_init();

8
src/mainboard/hp/dl145_g3/romstage.c
View File

@ -25,9 +25,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define ASSEMBLY 1
#define RAMINIT_SYSINFO 1
#define K8_ALLOCATE_IO_RANGE 1
@ -60,7 +57,6 @@
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#include "lib/ramtest.c"
@ -79,7 +75,6 @@
#include "superio/serverengines/pilot/pilot_early_init.c"
#include "superio/nsc/pc87417/pc87417_early_serial.c"
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/debug.c"
@ -139,7 +134,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#define DIMM6 0x56
#define DIMM7 0x57
#include "cpu/amd/car/copy_and_run.c"
#include "cpu/amd/car/post_cache_as_ram.c"
@ -218,7 +212,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
pc87417_enable_dev(RTC_DEV);
}
if (bist == 0) {
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
}
@ -232,7 +225,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
console_init();
// setup_early_ipmi_serial();
pilot_early_init(SERIAL_DEV); //config port is being taken from SERIAL_DEV

4
src/mainboard/hp/e_vectra_p2706t/romstage.c
View File

@ -18,9 +18,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define ASSEMBLY 1
#include <stdint.h>
#include <device/pci_def.h>
#include <arch/io.h>
@ -66,3 +63,4 @@ static void main(unsigned long bist)
sdram_enable();
/* ram_check(0, 640 * 1024); */
}

5
src/mainboard/ibm/e325/romstage.c
View File

@ -1,5 +1,3 @@
#define ASSEMBLY 1
#include <stdint.h>
#include <string.h>
@ -59,7 +57,6 @@ static void memreset(int controllers, const struct mem_controller *ctrl)
}
}
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
/* nothing to do */
@ -92,7 +89,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "cpu/amd/model_fxx/init_cpus.c"
#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
@ -167,3 +163,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_cache_as_ram();
}

4
src/mainboard/ibm/e326/romstage.c
View File

@ -1,5 +1,3 @@
#define ASSEMBLY 1
#include <stdint.h>
#include <string.h>
@ -59,7 +57,6 @@ static void memreset(int controllers, const struct mem_controller *ctrl)
}
}
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
/* nothing to do */
@ -166,3 +163,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_cache_as_ram();
}

4
src/mainboard/iei/juki-511p/romstage.c
View File

@ -18,9 +18,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define ASSEMBLY 1
#include <stdint.h>
#include <device/pci_def.h>
#include <arch/io.h>
@ -61,3 +58,4 @@ static void main(unsigned long bist)
/* Check RAM. */
/* ram_check(0x00000000, 640 * 1024); */
}

4
src/mainboard/iei/nova4899r/romstage.c
View File

@ -18,9 +18,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define ASSEMBLY 1
#include <stdint.h>
#include <device/pci_def.h>
#include <arch/io.h>
@ -56,3 +53,4 @@ static void main(unsigned long bist)
/* Check RAM. */
/* ram_check(0x00000000, 640 * 1024); */
}

4
src/mainboard/iei/pcisa-lx-800-r10/romstage.c
View File

@ -18,9 +18,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define ASSEMBLY 1
#include <stdint.h>
#include <device/pci_def.h>
#include <arch/io.h>
@ -135,3 +132,4 @@ void cache_as_ram_main(void)
/* Memory is setup. Return to cache_as_ram.inc and continue to boot. */
return;
}

2
src/mainboard/intel/d945gclf/romstage.c
View File

@ -19,7 +19,6 @@
// __PRE_RAM__ means: use "unsigned" for device, not a struct.
/* Configuration of the i945 driver */
#define CHIPSET_I945GC 1
#define CHANNEL_XOR_RANDOMIZATION 1
@ -98,7 +97,6 @@ static void ich7_enable_lpc(void)
pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x007c0681);
}
/* This box has two superios, so enabling serial becomes slightly excessive.
* We disable a lot of stuff to make sure that there are no conflicts between
* the two. Also set up the GPIOs from the beginning. This is the "no schematic

3
src/mainboard/intel/eagleheights/romstage.c
View File

@ -20,8 +20,6 @@
* MA 02110-1301 USA
*/
#include <delay.h>
#include <stdint.h>
@ -236,3 +234,4 @@ void real_main(unsigned long bist)
/* Use Intel Core (not Core 2) code for CAR init, any CPU might be used. */
#include "cpu/intel/model_6ex/cache_as_ram_disable.c"

4
src/mainboard/intel/jarrell/romstage.c
View File

@ -1,5 +1,3 @@
#define ASSEMBLY 1
#include <stdint.h>
#include <device/pci_def.h>
#include <arch/io.h>
@ -53,7 +51,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "lib/generic_sdram.c"
#include "debug.c"
static void main(unsigned long bist)
{
/*
@ -150,3 +147,4 @@ static void main(unsigned long bist)
}
#endif
}

4
src/mainboard/intel/mtarvon/romstage.c
View File

@ -18,8 +18,6 @@
*
*/
#define ASSEMBLY 1
#include <stdint.h>
#include <stdlib.h>
#include <device/pci_def.h>
@ -61,7 +59,6 @@ static inline int spd_read_byte(u16 device, u8 address)
#include "lib/generic_sdram.c"
#include "../jarrell/debug.c"
static void main(unsigned long bist)
{
msr_t msr;
@ -126,3 +123,4 @@ static void main(unsigned long bist)
ram_check(0, 1024 * 1024);
}

3
src/mainboard/intel/truxton/romstage.c
View File

@ -18,8 +18,6 @@
*
*/
#define ASSEMBLY 1
#include <stdint.h>
#include <stdlib.h>
#include <device/pci_def.h>
@ -113,3 +111,4 @@ static void main(unsigned long bist)
ram_verify(0x00000000, 0x02000000);
#endif
}

5
src/mainboard/intel/xe7501devkit/romstage.c
View File

@ -1,6 +1,3 @@
#define ASSEMBLY 1
#include <stdint.h>
#include <device/pci_def.h>
#include <arch/io.h>
@ -44,7 +41,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "northbridge/intel/e7501/reset_test.c"
#include "lib/generic_sdram.c"
// This function MUST appear last (ROMCC limitation)
static void main(unsigned long bist)
{
@ -92,3 +88,4 @@ static void main(unsigned long bist)
// if the following line is removed.
print_debug("SDRAM is up.\r\n");
}

8
src/mainboard/iwill/dk8_htx/romstage.c
View File

@ -1,6 +1,3 @@
#define ASSEMBLY 1
#define RAMINIT_SYSINFO 1
#define CACHE_AS_RAM_ADDRESS_DEBUG 0
@ -39,7 +36,6 @@
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
@ -117,7 +113,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#define DIMM6 0x56
#define DIMM7 0x57
#include "cpu/amd/car/copy_and_run.c"
#include "cpu/amd/car/post_cache_as_ram.c"
@ -193,7 +188,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* it will set up chains and store link pair for optimization later */
ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
#if K8_SET_FIDVID == 1
{
@ -245,7 +239,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
init_timer(); // Need to use TMICT to synconize FID/VID
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
#if 0
dump_pci_devices();
#endif
@ -253,3 +246,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
}

8
src/mainboard/iwill/dk8s2/romstage.c
View File

@ -1,6 +1,3 @@
#define ASSEMBLY 1
#define RAMINIT_SYSINFO 1
#define CACHE_AS_RAM_ADDRESS_DEBUG 0
@ -39,7 +36,6 @@
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
@ -117,7 +113,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#define DIMM6 0x56
#define DIMM7 0x57
#include "cpu/amd/car/copy_and_run.c"
#include "cpu/amd/car/post_cache_as_ram.c"
@ -193,7 +188,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* it will set up chains and store link pair for optimization later */
ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
#if K8_SET_FIDVID == 1
{
@ -245,7 +239,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
init_timer(); // Need to use TMICT to synconize FID/VID
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
#if 0
dump_pci_devices();
#endif
@ -253,3 +246,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
}

7
src/mainboard/iwill/dk8x/romstage.c
View File

@ -1,6 +1,3 @@
#define ASSEMBLY 1
#define RAMINIT_SYSINFO 1
#define CACHE_AS_RAM_ADDRESS_DEBUG 0
@ -116,7 +113,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#define DIMM6 0x56
#define DIMM7 0x57
#include "cpu/amd/car/copy_and_run.c"
#include "cpu/amd/car/post_cache_as_ram.c"
@ -192,7 +188,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* it will set up chains and store link pair for optimization later */
ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
#if K8_SET_FIDVID == 1
{
@ -244,7 +239,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
init_timer(); // Need to use TMICT to synconize FID/VID
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
#if 0
dump_pci_devices();
#endif
@ -252,3 +246,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
}

4
src/mainboard/jetway/j7f24/romstage.c
View File

@ -19,9 +19,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define ASSEMBLY 1
#include <stdint.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
@ -128,3 +125,4 @@ static void main(unsigned long bist)
print_spew("Leaving romstage.c:main()\r\n");
}

2
src/mainboard/kontron/986lcd-m/romstage.c
View File

@ -19,7 +19,6 @@
// __PRE_RAM__ means: use "unsigned" for device, not a struct.
/* Configuration of the i945 driver */
#define CHIPSET_I945GM 1
/* Usually system firmware turns off system memory clock signals to
@ -112,7 +111,6 @@ static void ich7_enable_lpc(void)
pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000301);
}
/* This box has two superios, so enabling serial becomes slightly excessive.
* We disable a lot of stuff to make sure that there are no conflicts between
* the two. Also set up the GPIOs from the beginning. This is the "no schematic

5
src/mainboard/kontron/kt690/romstage.c
View File

@ -18,9 +18,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define ASSEMBLY 1
#define RAMINIT_SYSINFO 1
#define K8_SET_FIDVID 1
#define QRANK_DIMM_SUPPORT 1
@ -182,7 +179,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
rs690_htinit();
printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset);
if (needs_reset) {
print_info("ht reset -\r\n");
soft_reset();
@ -201,3 +197,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_cache_as_ram();
}

7
src/mainboard/lippert/frontrunner/romstage.c
View File

@ -1,6 +1,3 @@
#define ASSEMBLY 1
#include <stdint.h>
#include <device/pci_def.h>
#include <arch/io.h>
@ -70,12 +67,10 @@ static void msr_init(void)
__builtin_wrmsr(0x40000029, 0x7bf00100, 0x2000000f);
__builtin_wrmsr(0x4000002d, 0xff030003, 0x20000000);
__builtin_wrmsr(0x50002001, 0x27, 0x0);
__builtin_wrmsr(0x4c002001, 0x1, 0x0);
}
static void main(unsigned long bist)
{
static const struct mem_controller memctrl [] = {
@ -104,7 +99,6 @@ static void main(unsigned long bist)
outb( 0x87, 0x4E); //enter SuperIO configuration mode
outb( 0x87, 0x4E);
outb(0x20, 0x4e);
temp = inb(0x4f);
print_debug_hex8(temp);
@ -134,3 +128,4 @@ static void main(unsigned long bist)
// ram_check(0x00000000, 640*1024);
}

4
src/mainboard/lippert/roadrunner-lx/romstage.c
View File

@ -21,9 +21,6 @@
/* Based on romstage.c from AMD's DB800 and DBM690T mainboards. */
#define ASSEMBLY 1
#include <stdlib.h>
#include <stdint.h>
#include <device/pci_def.h>
@ -167,3 +164,4 @@ void cache_as_ram_main(void)
/* Memory is setup. Return to cache_as_ram.inc and continue to boot. */
return;
}

4
src/mainboard/lippert/spacerunner-lx/romstage.c
View File

@ -21,9 +21,6 @@
/* Based on romstage.c from AMD's DB800 and DBM690T mainboards. */
#define ASSEMBLY 1
#include <stdlib.h>
#include <stdint.h>
#include <spd.h>
@ -236,3 +233,4 @@ void cache_as_ram_main(void)
/* Memory is setup. Return to cache_as_ram.inc and continue to boot. */
return;
}

4
src/mainboard/mitac/6513wu/romstage.c
View File

@ -18,9 +18,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define ASSEMBLY 1
#include <stdint.h>
#include <stdlib.h>
#include <device/pci_def.h>
@ -67,3 +64,4 @@ static void main(unsigned long bist)
sdram_enable();
/* ram_check(0, 640 * 1024); */
}

4
src/mainboard/msi/ms6119/romstage.c
View File

@ -18,9 +18,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define ASSEMBLY 1
#include <stdint.h>
#include <stdlib.h>
#include <device/pci_def.h>
@ -71,3 +68,4 @@ static void main(unsigned long bist)
sdram_enable();
/* ram_check(0, 640 * 1024); */
}

4
src/mainboard/msi/ms6147/romstage.c
View File

@ -18,9 +18,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define ASSEMBLY 1
#include <stdint.h>
#include <stdlib.h>
#include <device/pci_def.h>
@ -78,3 +75,4 @@ static void main(unsigned long bist)
ram_check(0x00100000, 0x07ffffff); /* 1MB to 128MB- */
#endif
}

4
src/mainboard/msi/ms6156/romstage.c
View File

@ -18,9 +18,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define ASSEMBLY 1
#include <stdint.h>
#include <stdlib.h>
#include <device/pci_def.h>
@ -71,3 +68,4 @@ static void main(unsigned long bist)
sdram_enable();
/* ram_check(0, 640 * 1024); */
}

4
src/mainboard/msi/ms6178/romstage.c
View File

@ -18,9 +18,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define ASSEMBLY 1
#include <stdint.h>
#include <device/pci_def.h>
#include <arch/io.h>
@ -67,3 +64,4 @@ static void main(unsigned long bist)
sdram_enable();
/* ram_check(0, 640 * 1024); */
}

4
src/mainboard/msi/ms7135/romstage.c
View File

@ -22,9 +22,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define ASSEMBLY 1
#define SERIAL_DEV PNP_DEV(0x4e, W83627HF_SP1)
/* Used by raminit. */
@ -199,3 +196,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_cache_as_ram();
}

3
src/mainboard/msi/ms7260/romstage.c
View File

@ -20,9 +20,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define ASSEMBLY 1
// #define CACHE_AS_RAM_ADDRESS_DEBUG 1
// #define RAM_TIMING_DEBUG 1
// #define DQS_TRAIN_DEBUG 1

10
src/mainboard/msi/ms9185/romstage.c
View File

@ -23,9 +23,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define ASSEMBLY 1
#define RAMINIT_SYSINFO 1
#define CACHE_AS_RAM_ADDRESS_DEBUG 0
@ -72,7 +69,6 @@ static void post_code(uint8_t value) {
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
@ -112,8 +108,6 @@ static inline void change_i2c_mux(unsigned device)
}
#endif
static inline int spd_read_byte(unsigned device, unsigned address)
{
return smbus_read_byte(device, address);
@ -145,7 +139,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#define DIMM6 0x56
#define DIMM7 0x57
#include "cpu/amd/car/copy_and_run.c"
#include "cpu/amd/car/post_cache_as_ram.c"
@ -231,7 +224,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
bcm5785_early_setup();
#if 0
//it your CPU min fid is 1G, you can change HT to 1G and FID to max one time.
needs_reset = optimize_link_coherent_ht();
@ -315,5 +307,5 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_cache_as_ram();
}

6
src/mainboard/msi/ms9282/romstage.c
View File

@ -22,9 +22,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define ASSEMBLY 1
#define RAMINIT_SYSINFO 1
#define CACHE_AS_RAM_ADDRESS_DEBUG 0
@ -136,7 +133,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
static void sio_setup(void)
{
@ -152,7 +148,6 @@ static void sio_setup(void)
dword |= (1<<0);
pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
}
//CPU 1 mem is on SMBUS_HUB channel 2, and CPU 2 mem is on channel 1.
@ -243,3 +238,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_cache_as_ram();
}

3
src/mainboard/msi/ms9652_fam10/romstage.c
View File

@ -19,9 +19,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define ASSEMBLY 1
#define RAMINIT_SYSINFO 1
#define FAM10_SCAN_PCI_BUS 0

4
src/mainboard/nec/powermate2000/romstage.c
View File

@ -18,9 +18,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define ASSEMBLY 1
#include <stdint.h>
#include <device/pci_def.h>
#include <arch/io.h>
@ -60,3 +57,4 @@ static void main(unsigned long bist)
sdram_enable();
/* ram_check(0, 640 * 1024); */
}

5
src/mainboard/newisys/khepri/romstage.c
View File

@ -3,7 +3,6 @@
* Adapted by Stefan Reinauer <stepan@coresystems.de>
* Additional (C) 2007 coresystems GmbH
*/
#define ASSEMBLY 1
#include <stdint.h>
@ -100,14 +99,12 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#endif
#include "cpu/amd/dualcore/dualcore.c"
#include "cpu/amd/car/copy_and_run.c"
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/model_fxx/init_cpus.c"
#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
@ -175,7 +172,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
soft_reset();
}
allow_all_aps_stop(bsp_apicid);
nodes = get_nodes();
@ -194,3 +190,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_cache_as_ram();
}

5
src/mainboard/nvidia/l1_2pvv/romstage.c
View File

@ -19,9 +19,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define ASSEMBLY 1
#define RAMINIT_SYSINFO 1
#define K8_ALLOCATE_IO_RANGE 1
@ -146,7 +143,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
static void sio_setup(void)
{
@ -212,7 +208,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
#if CONFIG_USBDEBUG_DIRECT
mcp55_enable_usbdebug_direct(DBGP_DEFAULT);
early_usbdebug_direct_init();

7
src/mainboard/olpc/btest/romstage.c
View File

@ -1,6 +1,3 @@
#define ASSEMBLY 1
#include <stdint.h>
#include <device/pci_def.h>
#include <arch/io.h>
@ -38,9 +35,6 @@ static inline unsigned int fls(unsigned int x)
return r;
}
/* sdram parameters for OLPC:
row address = 13
col address = 9
@ -192,3 +186,4 @@ static void main(unsigned long bist)
/* Check all of memory */
//ram_check(0x00000000, 640*1024);
}

7
src/mainboard/olpc/rev_a/romstage.c
View File

@ -1,6 +1,3 @@
#define ASSEMBLY 1
#include <stdint.h>
#include <device/pci_def.h>
#include <arch/io.h>
@ -38,9 +35,6 @@ static inline unsigned int fls(unsigned int x)
return r;
}
/* sdram parameters for OLPC:
row address = 13
col address = 9
@ -192,3 +186,4 @@ static void main(unsigned long bist)
/* Check all of memory */
//ram_check(0x00000000, 640*1024);
}

4
src/mainboard/pcengines/alix1c/romstage.c
View File

@ -17,9 +17,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define ASSEMBLY 1
#include <stdint.h>
#include <spd.h>
#include <device/pci_def.h>
@ -210,3 +207,4 @@ void cache_as_ram_main(void)
void done_cache_as_ram_main(void);
done_cache_as_ram_main();
}

4
src/mainboard/rca/rm4100/romstage.c
View File

@ -18,9 +18,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define ASSEMBLY 1
#include <stdint.h>
#include <stdlib.h>
#include <device/pci_def.h>
@ -133,3 +130,4 @@ static void main(unsigned long bist)
/* ram_check(0, 640 * 1024); */
/* ram_check(64512 * 1024, 65536 * 1024); */
}

3
src/mainboard/roda/rk886ex/romstage.c
View File

@ -21,7 +21,6 @@
// __PRE_RAM__ means: use "unsigned" for device, not a struct.
/* Configuration of the i945 driver */
#define CHIPSET_I945GM 1
#define CHANNEL_XOR_RANDOMIZATION 1
@ -79,7 +78,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
return smbus_read_byte(device, address);
}
#include "northbridge/intel/i945/raminit.h"
#include "northbridge/intel/i945/raminit.c"
#include "northbridge/intel/i945/errata.c"
@ -102,7 +100,6 @@ static void ich7_enable_lpc(void)
pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x00040069);
}
/* This box has two superios, so enabling serial becomes slightly excessive.
* We disable a lot of stuff to make sure that there are no conflicts between
* the two. Also set up the GPIOs from the beginning. This is the "no schematic

4
src/mainboard/soyo/sy-6ba-plus-iii/romstage.c
View File

@ -18,9 +18,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define ASSEMBLY 1
#include <stdint.h>
#include <device/pci_def.h>
#include <arch/io.h>
@ -71,3 +68,4 @@ static void main(unsigned long bist)
sdram_enable();
/* ram_check(0, 640 * 1024); */
}

8
src/mainboard/sunw/ultra40/romstage.c
View File

@ -1,7 +1,3 @@
#define ASSEMBLY 1
#define K8_ALLOCATE_IO_RANGE 1
#define QRANK_DIMM_SUPPORT 1
@ -78,7 +74,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
return smbus_read_byte(device, address);
}
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "lib/generic_sdram.c"
@ -111,11 +106,9 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "cpu/amd/model_fxx/init_cpus.c"
#include "southbridge/nvidia/ck804/ck804_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
static void sio_setup(void)
{
@ -217,3 +210,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_cache_as_ram();
}

3
src/mainboard/supermicro/h8dme/romstage.c
View File

@ -16,9 +16,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define ASSEMBLY 1
#define RAMINIT_SYSINFO 1
#define K8_ALLOCATE_IO_RANGE 1

5
src/mainboard/supermicro/h8dmr/romstage.c
View File

@ -19,9 +19,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define ASSEMBLY 1
#define RAMINIT_SYSINFO 1
#define K8_ALLOCATE_IO_RANGE 1
@ -77,7 +74,6 @@
#include "cpu/amd/mtrr/amd_earlymtrr.c"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
@ -135,7 +131,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
static void sio_setup(void)
{

7
src/mainboard/supermicro/h8dmr_fam10/romstage.c
View File

@ -19,9 +19,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define ASSEMBLY 1
#define RAMINIT_SYSINFO 1
#define FAM10_SCAN_PCI_BUS 0
@ -70,7 +67,6 @@
#include "cpu/amd/mtrr/amd_earlymtrr.c"
#include "northbridge/amd/amdfam10/setup_resource_map.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
@ -126,7 +122,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
#include "northbridge/amd/amdfam10/early_ht.c"
static void sio_setup(void)
{
@ -194,7 +189,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
console_init();
printk(BIOS_DEBUG, "\n");
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
@ -293,7 +287,6 @@ post_code(0x3E);
post_code(0x40);
printk(BIOS_DEBUG, "raminit_amdmct()\n");
raminit_amdmct(sysinfo);
post_code(0x41);

6
src/mainboard/supermicro/h8qme_fam10/romstage.c
View File

@ -19,9 +19,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define ASSEMBLY 1
#define RAMINIT_SYSINFO 1
#define FAM10_SCAN_PCI_BUS 0
@ -71,7 +68,6 @@
#include "cpu/amd/mtrr/amd_earlymtrr.c"
#include "northbridge/amd/amdfam10/setup_resource_map.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
@ -130,7 +126,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
#include "northbridge/amd/amdfam10/early_ht.c"
static void sio_setup(void)
{
@ -337,7 +332,6 @@ post_code(0x3E);
post_code(0x40);
printk(BIOS_DEBUG, "raminit_amdmct()\n");
raminit_amdmct(sysinfo);
post_code(0x41);

5
src/mainboard/supermicro/x6dai_g/romstage.c
View File

@ -1,5 +1,3 @@
#define ASSEMBLY 1
#include <stdint.h>
#include <device/pci_def.h>
#include <arch/io.h>
@ -24,7 +22,6 @@
#include "northbridge/intel/e7525/memory_initialized.c"
#include "cpu/x86/bist.h"
#define SIO_GPIO_BASE 0x680
#define SIO_XBUS_BASE 0x4880
@ -55,7 +52,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "northbridge/intel/e7525/raminit.c"
#include "lib/generic_sdram.c"
static void main(unsigned long bist)
{
/*
@ -139,3 +135,4 @@ static void main(unsigned long bist)
}
#endif
}

5
src/mainboard/supermicro/x6dhe_g/romstage.c
View File

@ -1,5 +1,3 @@
#define ASSEMBLY 1
#include <stdint.h>
#include <device/pci_def.h>
#include <arch/io.h>
@ -25,7 +23,6 @@
#include "northbridge/intel/e7520/memory_initialized.c"
#include "cpu/x86/bist.h"
#define SIO_GPIO_BASE 0x680
#define SIO_XBUS_BASE 0x4880
@ -56,7 +53,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "northbridge/intel/e7520/raminit.c"
#include "lib/generic_sdram.c"
static void main(unsigned long bist)
{
/*
@ -150,3 +146,4 @@ static void main(unsigned long bist)
}
#endif
}

5
src/mainboard/supermicro/x6dhe_g2/romstage.c
View File

@ -1,5 +1,3 @@
#define ASSEMBLY 1
#include <stdint.h>
#include <device/pci_def.h>
#include <arch/io.h>
@ -25,7 +23,6 @@
#include "northbridge/intel/e7520/memory_initialized.c"
#include "cpu/x86/bist.h"
#define SIO_GPIO_BASE 0x680
#define SIO_XBUS_BASE 0x4880
@ -56,7 +53,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "northbridge/intel/e7520/raminit.c"
#include "lib/generic_sdram.c"
static void main(unsigned long bist)
{
/*
@ -151,3 +147,4 @@ static void main(unsigned long bist)
}
#endif
}

5
src/mainboard/supermicro/x6dhr_ig/romstage.c
View File

@ -1,5 +1,3 @@
#define ASSEMBLY 1
#include <stdint.h>
#include <device/pci_def.h>
#include <arch/io.h>
@ -25,7 +23,6 @@
#include "northbridge/intel/e7520/memory_initialized.c"
#include "cpu/x86/bist.h"
#define SIO_GPIO_BASE 0x680
#define SIO_XBUS_BASE 0x4880
@ -57,7 +54,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "northbridge/intel/e7520/raminit.c"
#include "lib/generic_sdram.c"
static void main(unsigned long bist)
{
/*
@ -152,3 +148,4 @@ static void main(unsigned long bist)
}
#endif
}

5
src/mainboard/supermicro/x6dhr_ig2/romstage.c
View File

@ -1,5 +1,3 @@
#define ASSEMBLY 1
#include <stdint.h>
#include <device/pci_def.h>
#include <arch/io.h>
@ -25,7 +23,6 @@
#include "northbridge/intel/e7520/memory_initialized.c"
#include "cpu/x86/bist.h"
#define SIO_GPIO_BASE 0x680
#define SIO_XBUS_BASE 0x4880
@ -57,7 +54,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "northbridge/intel/e7520/raminit.c"
#include "lib/generic_sdram.c"
static void main(unsigned long bist)
{
/*
@ -152,3 +148,4 @@ static void main(unsigned long bist)
}
#endif
}

5
src/mainboard/technexion/tim5690/romstage.c
View File

@ -17,9 +17,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define ASSEMBLY 1
#define RAMINIT_SYSINFO 1
#define K8_SET_FIDVID 1
#define QRANK_DIMM_SUPPORT 1
@ -186,7 +183,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
rs690_htinit();
printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset);
if (needs_reset) {
print_info("ht reset -\r\n");
soft_reset();
@ -214,3 +210,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_cache_as_ram();
}

6
src/mainboard/technexion/tim8690/romstage.c
View File

@ -17,9 +17,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define ASSEMBLY 1
#define RAMINIT_SYSINFO 1
#define K8_SET_FIDVID 1
#define QRANK_DIMM_SUPPORT 1
@ -111,7 +108,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
struct cpuid_result cpuid1;
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
@ -181,7 +177,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
rs690_htinit();
printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset);
if (needs_reset) {
print_info("ht reset -\r\n");
soft_reset();
@ -200,3 +195,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_cache_as_ram();
}

2
src/mainboard/technologic/ts5300/romstage.c
View File

@ -4,8 +4,6 @@
* (c) 2006 coresystems GmbH
*/
#define ASSEMBLY 1
#define ASM_CONSOLE_LOGLEVEL 6
#include <stdint.h>
#include <device/pci_def.h>

4
src/mainboard/televideo/tc7020/romstage.c
View File

@ -18,9 +18,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define ASSEMBLY 1
#include <stdint.h>
#include <device/pci_def.h>
#include <arch/io.h>
@ -55,3 +52,4 @@ static void main(unsigned long bist)
/* Check whether RAM works. */
/* ram_check(0, 640 * 1024); */
}

4
src/mainboard/thomson/ip1000/romstage.c
View File

@ -18,9 +18,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define ASSEMBLY 1
#include <stdint.h>
#include <stdlib.h>
#include <device/pci_def.h>
@ -135,3 +132,4 @@ static void main(unsigned long bist)
/* ram_check(0, 640 * 1024); */
/* ram_check(64512 * 1024, 65536 * 1024); */
}

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