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Add AMD SB800 southbridge CIMx code. 

The main CIMx code is in a src/vendorcode directory and should not be
changed with regard to coding style etc. in order to remain easily syncable
with the "upstream" AMD code.

Signed-off-by: Kerry She <Kerry.she@amd.com>
Acked-by: Stefan Reinauer <stepan@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6229 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Kerry She 2011-01-01 17:44:07 +00:00 committed by Uwe Hermann
parent 123edb0f68
commit 799fed98ea
40 changed files with 10730 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
Makefile
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@ -126,6 +126,7 @@ TARGETS-y :=
BUILD-y := src/lib src/boot src/console src/devices src/southbridge src/northbridge src/superio src/drivers
BUILD-y += util/cbfstool util/sconfig
BUILD-$(CONFIG_ARCH_X86) += src/pc80
BUILD-y += src/vendorcode
ifneq ($(CONFIG_LOCALVERSION),"")
COREBOOT_EXTRA_VERSION := -$(call strip_quotes,$(CONFIG_LOCALVERSION))

1
src/cpu/amd/model_10xxx/init_cpus.c
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@ -27,6 +27,7 @@
#include <cpu/x86/mtrr/earlymtrr.c>
#include <northbridge/amd/amdfam10/raminit_amdmct.c>
#include <reset.h>
static void prep_fid_change(void);
static void init_fidvid_stage2(u32 apicid, u32 nodeid);

1
src/vendorcode/Makefile.inc Normal file
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@ -0,0 +1 @@
subdirs-y += amd

3
src/vendorcode/amd/cimx/lib/Makefile.inc Normal file
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@ -0,0 +1,3 @@
romstage-y += amdlib32.c
ramstage-y += amdlib32.c

84
src/vendorcode/amd/cimx/lib/amdlib32.c Normal file
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@ -0,0 +1,84 @@
#include "amdlib32.h"
UINT8 ReadIo8 (IN UINT16 port)
{
UINT8 value;
__asm__ __volatile__ ("inb %w1, %b0" : "=a"(value) : "Nd" (port));
return value;
}
UINT16 ReadIo16 (IN UINT16 port)
{
UINT16 value;
__asm__ __volatile__ ("inw %w1, %w0" : "=a"(value) : "Nd" (port));
return value;
}
UINT32 ReadIo32 (IN UINT16 port)
{
UINT32 value;
__asm__ __volatile__ ("inl %w1, %0" : "=a"(value) : "Nd" (port));
return value;
}
VOID WriteIo8 (IN UINT16 port, IN UINT8 value)
{
__asm__ __volatile__ ("outb %b0, %w1" : : "a" (value), "Nd" (port));
}
VOID WriteIo16 (IN UINT16 port, IN UINT16 value)
{
__asm__ __volatile__ ("outw %w0, %w1" : : "a" (value), "Nd" (port));
}
VOID WriteIo32 (IN UINT16 port, IN UINT32 value)
{
__asm__ __volatile__ ("outl %0, %w1" : : "a" (value), "Nd" (port));
}
UINT64 ReadTSC(VOID)
{
struct tsc_struct {
unsigned lo;
unsigned hi;
} res;
UINT64 ret;
__asm__ __volatile__ (
"rdtsc"
: "=a" (res.lo), "=d"(res.hi) /* outputs */
);
ret = res.hi;
ret <<= 32;
ret |= res.lo;
return ret;
}
VOID CpuidRead(IN UINT32 op, IN OUT SB_CPUID_DATA* Data)
{
asm volatile(
"cpuid"
: "=a" (Data->EAX_Reg),
"=b" (Data->EBX_Reg),
"=c" (Data->ECX_Reg),
"=d" (Data->EDX_Reg)
: "0" (op));
}
static inline unsigned int cpuid_ecx(unsigned int op)
{
unsigned int eax, ecx;
__asm__("cpuid"
: "=a" (eax), "=c" (ecx)
: "0" (op)
: "ebx", "edx" );
return ecx;
}
//static inline unsigned get_core_num(void)
UINT8 ReadNumberOfCpuCores(VOID)
{
return (cpuid_ecx(0x80000008) & 0xff);
}

16
src/vendorcode/amd/cimx/lib/amdlib32.h Normal file
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@ -0,0 +1,16 @@
#ifndef _AMDLIB32_H_
#define _AMDLIB32_H_
#include "cbtypes.h"
#include "Amd.h"
UINT8 ReadIo8 (IN UINT16 port);
UINT16 ReadIo16 (IN UINT16 port);
UINT32 ReadIo32 (IN UINT16 port);
VOID WriteIo8 (IN UINT16 port, IN UINT8 value);
VOID WriteIo16 (IN UINT16 port, IN UINT16 value);
VOID WriteIo32 (IN UINT16 port, IN UINT32 value);
UINT64 ReadTSC(VOID);
VOID CpuidRead(IN UINT32 op, IN OUT SB_CPUID_DATA* Data);
UINT8 ReadNumberOfCpuCores(VOID);
#endif //_AMDLIB32_H_

158
src/vendorcode/amd/cimx/sb800/ACPILIB.c Normal file
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@ -0,0 +1,158 @@
/*
*****************************************************************************
*
* This file is part of the coreboot project.
*
* Copyright (C) 2010 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
* ***************************************************************************
*
*/
#include "SBPLATFORM.h"
//
//
// Routine Description:
//
// Locate ACPI table
//
// Arguments:
//
// Signature - table signature
//
//Returns:
//
// pointer to ACPI table
//
//
VOID*
ACPI_LocateTable (
IN UINT32 Signature
)
{
UINT32 i;
UINT32* RsdPtr;
UINT32* Rsdt;
UINTN tableOffset;
DESCRIPTION_HEADER* CurrentTable;
RsdPtr = (UINT32*) (UINTN)0xe0000;
Rsdt = NULL;
do {
//if ( *RsdPtr == ' DSR' && *(RsdPtr + 1) == ' RTP' ) { //gcc multi-character character constant warning
if ( *RsdPtr == 0x20445352 && *(RsdPtr + 1) == 0x20525450) {
Rsdt = (UINT32*) (UINTN) ((RSDP*)RsdPtr)->RsdtAddress;
break;
}
RsdPtr += 4;
} while ( RsdPtr <= (UINT32*) (UINTN)0xffff0 );
if ( Rsdt != NULL && ACPI_GetTableChecksum (Rsdt) == 0 ) {
for ( i = 0; i < (((DESCRIPTION_HEADER*)Rsdt)->Length - sizeof (DESCRIPTION_HEADER)) / 4; i++ ) {
tableOffset = *(UINTN*) ((UINT8*)Rsdt + sizeof (DESCRIPTION_HEADER) + i * 4);
CurrentTable = (DESCRIPTION_HEADER*)tableOffset;
if ( CurrentTable->Signature == Signature ) {
return CurrentTable;
}
}
}
return NULL;
}
//
//
// Routine Description:
//
// Update table checksum
//
// Arguments:
//
// TablePtr - table pointer
//
// Returns:
//
// none
//
//
VOID
ACPI_SetTableChecksum (
IN VOID* TablePtr
)
{
UINT8 Checksum;
Checksum = 0;
((DESCRIPTION_HEADER*)TablePtr)->Checksum = 0;
Checksum = ACPI_GetTableChecksum (TablePtr);
((DESCRIPTION_HEADER*)TablePtr)->Checksum = (UINT8)(0x100 - Checksum);
}
//
//
// Routine Description:
//
// Get table checksum
//
// Arguments:
//
// TablePtr - table pointer
//
// Returns:
//
// none
//
//
UINT8
ACPI_GetTableChecksum (
IN VOID* TablePtr
)
{
return GetByteSum (TablePtr, ((DESCRIPTION_HEADER*)TablePtr)->Length);
}
UINT8
GetByteSum (
IN VOID* pData,
IN UINT32 Length
)
{
UINT32 i;
UINT8 Checksum;
Checksum = 0;
for ( i = 0; i < Length; i++ ) {
Checksum = Checksum + (*((UINT8*)pData + i));
}
return Checksum;
}
VOID
GetSbAcpiMmioBase (
OUT UINT32* AcpiMmioBase
)
{
UINT32 Value16;
ReadPMIO (SB_PMIOA_REG24 + 2, AccWidthUint16, &Value16);
*AcpiMmioBase = Value16 << 16;
}
VOID
GetSbAcpiPmBase (
OUT UINT16* AcpiPmBase
)
{
ReadPMIO (SB_PMIOA_REG60, AccWidthUint16, AcpiPmBase);
}

60
src/vendorcode/amd/cimx/sb800/ACPILIB.h Normal file
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@ -0,0 +1,60 @@
/*
*****************************************************************************
*
* This file is part of the coreboot project.
*
* Copyright (C) 2010 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
* ***************************************************************************
*
*/
/**
* RSDP - ACPI 2.0 table RSDP
*/
typedef struct _RSDP
{
UINT64 Signature; /* RSDP signature "RSD PTR" */
UINT8 Checksum; /* checksum of the first 20 bytes */
UINT8 OEMID[6]; /* OEM ID, "LXBIOS" */
UINT8 Revision; /* 0 for APCI 1.0, 2 for ACPI 2.0 */
UINT32 RsdtAddress; /* physical address of RSDT */
UINT32 Length; /* total length of RSDP (including extended part) */
UINT64 XsdtAddress; /* physical address of XSDT */
UINT8 ExtendedChecksum; /* chechsum of whole table */
UINT8 Reserved[3];
} RSDP;
/**
* DESCRIPTION_HEADER - ACPI common table header
*/
typedef struct _DESCRIPTION_HEADER
{
UINT32 Signature; /* ACPI signature (4 ASCII characters) */
UINT32 Length; /* Length of table, in bytes, including header */
UINT8 Revision; /* ACPI Specification minor version # */
UINT8 Checksum; /* To make sum of entire table == 0 */
UINT8 OEMID[6]; /* OEM identification */
UINT8 OEMTableID[8]; /* OEM table identification */
UINT32 OEMRevision; /* OEM revision number */
UINT32 CreatorID; /* ASL compiler vendor ID */
UINT32 CreatorRevision; /* ASL compiler revision number */
} DESCRIPTION_HEADER;
VOID* ACPI_LocateTable (IN UINT32 Signature);
VOID ACPI_SetTableChecksum (IN VOID* TablePtr);
UINT8 ACPI_GetTableChecksum (IN VOID* TablePtr);
UINT8 GetByteSum (IN VOID* pData, IN UINT32 Length);

82
src/vendorcode/amd/cimx/sb800/AMDLIB.c Normal file
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@ -0,0 +1,82 @@
/*
*****************************************************************************
*
* This file is part of the coreboot project.
*
* Copyright (C) 2010 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
* ***************************************************************************
*
*/
#include "SBPLATFORM.h"
UINT8
getNumberOfCpuCores (
OUT VOID
)
{
UINT8 Result;
Result = 1;
Result = ReadNumberOfCpuCores ();
return Result;
}
UINT32
readAlink (
IN UINT32 Index
)
{
UINT32 Data;
WriteIO (ALINK_ACCESS_INDEX, AccWidthUint32, &Index);
ReadIO (ALINK_ACCESS_DATA, AccWidthUint32, &Data);
//Clear Index
Index = 0;
WriteIO (ALINK_ACCESS_INDEX, AccWidthUint32, &Index);
return Data;
}
VOID
writeAlink (
IN UINT32 Index,
IN UINT32 Data
)
{
WriteIO (ALINK_ACCESS_INDEX, AccWidthUint32 | S3_SAVE, &Index);
WriteIO (ALINK_ACCESS_DATA, AccWidthUint32 | S3_SAVE, &Data);
//Clear Index
Index = 0;
WriteIO (ALINK_ACCESS_INDEX, AccWidthUint32 | S3_SAVE, &Index);
}
VOID
rwAlink (
IN UINT32 Index,
IN UINT32 AndMask,
IN UINT32 OrMask
)
{
UINT32 AccesType;
AccesType = Index & 0xE0000000;
if (AccesType == (AXINDC << 29)) {
writeAlink ((SB_AX_INDXC_REG30 | AccesType), Index & 0x1FFFFFFF);
Index = (SB_AX_DATAC_REG34 | AccesType);
} else if (AccesType == (AXINDP << 29)) {
writeAlink ((SB_AX_INDXP_REG38 | AccesType), Index & 0x1FFFFFFF);
Index = (SB_AX_DATAP_REG3C | AccesType);
}
writeAlink (Index, (readAlink (Index) & AndMask) | OrMask );
}

142
src/vendorcode/amd/cimx/sb800/AMDSBLIB.c Normal file
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@ -0,0 +1,142 @@
/**
* @file
*
* Southbridge IO access common routine
*
*
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: CIMx-SB
* @e sub-project:
* @e \$Revision:$ @e \$Date:$
*
*/
/*
*****************************************************************************
*
* This file is part of the coreboot project.
*
* Copyright (C) 2010 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
* ***************************************************************************
*
*/
#include "SBPLATFORM.h"
/*----------------------------------------------------------------------------------------*/
/**
* SbStall - Delay routine
*
*
*
* @param[in] uSec
*
*/
VOID
SbStall (
IN UINT32 uSec
)
{
UINT16 timerAddr;
UINT32 startTime;
UINT32 elapsedTime;
ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG64, AccWidthUint16, &timerAddr);
if ( timerAddr == 0 ) {
uSec = uSec / 2;
while ( uSec != 0 ) {
ReadIO (0x80, AccWidthUint8, (UINT8 *) (&startTime));
uSec--;
}
} else {
ReadIO (timerAddr, AccWidthUint32, &startTime);
for ( ;; ) {
ReadIO (timerAddr, AccWidthUint32, &elapsedTime);
if ( elapsedTime < startTime ) {
elapsedTime = elapsedTime + 0xFFFFFFFF - startTime;
} else {
elapsedTime = elapsedTime - startTime;
}
if ( (elapsedTime * 28 / 100) > uSec ) {
break;
}
}
}
}
/*----------------------------------------------------------------------------------------*/
/**
* SbReset - Generate a reset command
*
*
*
* @param[in] OpFlag - Dummy
*
*/
VOID
SbReset (
IN UINT8 OpFlag
)
{
UINT8 Temp;
Temp = OpFlag;
RWIO (0xcf9, AccWidthUint8, 0x0, 0x06);
}
/*----------------------------------------------------------------------------------------*/
/**
* outPort80 - Send data to PORT 80 (debug port)
*
*
*
* @param[in] pcode - debug code (32 bits)
*
*/
VOID
outPort80 (
IN UINT32 pcode
)
{
WriteIO (0x80, AccWidthUint8, &pcode);
return;
}
/**
* AmdSbCopyMem - Memory copy
*
* @param[in] pDest - Destance address point
* @param[in] pSource - Source Address point
* @param[in] Length - Data length
*
*/
VOID
AmdSbCopyMem (
IN VOID* pDest,
IN VOID* pSource,
IN UINTN Length
)
{
UINTN i;
UINT8 *Ptr;
UINT8 *Source;
Ptr = (UINT8*)pDest;
Source = (UINT8*)pSource;
for (i = 0; i < Length; i++) {
*Ptr = *Source;
Source++;
Ptr++;
}
}

97
src/vendorcode/amd/cimx/sb800/AMDSBLIB.h Normal file
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@ -0,0 +1,97 @@
/**
* @file
*
* Southbridge IO access common routine define file
*
*
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: CIMx-SB
* @e sub-project:
* @e \$Revision:$ @e \$Date:$
*
*/
/*
*****************************************************************************
*
* This file is part of the coreboot project.
*
* Copyright (C) 2010 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
* ***************************************************************************
*
*/
//AMDSBLIB Routines
/**
* SbStall - Delay routine
*
*
*
* @param[in] uSec
*
*/
VOID SbStall (IN UINT32 uSec);
/**
* SbReset - Generate a reset command
*
*
*
* @param[in] OpFlag - Dummy
*
*/
VOID SbReset (IN UINT8 OpFlag);
/**
* outPort80 - Send data to PORT 80 (debug port)
*
*
*
* @param[in] pcode - debug code (32 bits)
*
*/
VOID outPort80 (IN UINT32 pcode);
/**
* getEfuseStatue - Get Efuse status
*
*
* @param[in] Value - Return Chip strap status
*
*/
VOID getEfuseStatus (IN VOID* Value);
/**
* AmdSbDispatcher - Dispatch Southbridge function
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
AGESA_STATUS AmdSbDispatcher (IN VOID *pConfig);
/**
* AmdSbCopyMem - Memory copy
*
* @param[in] pDest - Destance address point
* @param[in] pSource - Source Address point
* @param[in] Length - Data length
*
*/
VOID AmdSbCopyMem (IN VOID* pDest, IN VOID* pSource, IN UINTN Length);

502
src/vendorcode/amd/cimx/sb800/AZALIA.c Normal file
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@ -0,0 +1,502 @@
/**
* @file
*
* Config Southbridge HD Audio Controller
*
*
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: CIMx-SB
* @e sub-project:
* @e \$Revision:$ @e \$Date:$
*
*/
/*
*****************************************************************************
*
* This file is part of the coreboot project.
*
* Copyright (C) 2010 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
* ***************************************************************************
*
*/
#include "SBPLATFORM.h"
//
// Declaration of local functions
//
VOID configureAzaliaPinCmd (IN AMDSBCFG* pConfig, IN UINT32 ddBAR0, IN UINT8 dbChannelNum);
VOID configureAzaliaSetConfigD4Dword (IN CODECENTRY* tempAzaliaCodecEntryPtr, IN UINT32 ddChannelNum, IN UINT32 ddBAR0);
/**
* Pin Config for ALC880, ALC882 and ALC883.
*
*
*
*/
CODECENTRY AzaliaCodecAlc882Table[] =
{
{0x14, 0x01014010},
{0x15, 0x01011012},
{0x16, 0x01016011},
{0x17, 0x01012014},
{0x18, 0x01A19030},
{0x19, 0x411111F0},
{0x1a, 0x01813080},
{0x1b, 0x411111F0},
{0x1C, 0x411111F0},
{0x1d, 0x411111F0},
{0x1e, 0x01441150},
{0x1f, 0x01C46160},
{0xff, 0xffffffff}
};
/**
* Pin Config for ALC0262.
*
*
*
*/
CODECENTRY AzaliaCodecAlc262Table[] =
{
{0x14, 0x01014010},
{0x15, 0x411111F0},
{0x16, 0x411111F0},
{0x18, 0x01A19830},
{0x19, 0x02A19C40},
{0x1a, 0x01813031},
{0x1b, 0x02014C20},
{0x1c, 0x411111F0},
{0x1d, 0x411111F0},
{0x1e, 0x0144111E},
{0x1f, 0x01C46150},
{0xff, 0xffffffff}
};
/**
* Pin Config for ALC0269.
*
*
*
*/
CODECENTRY AzaliaCodecAlc269Table[] =
{
{0x12, 0x99A30960},
{0x14, 0x99130110},
{0x15, 0x0221401F},
{0x16, 0x99130120},
{0x18, 0x01A19850},
{0x19, 0x02A15951},
{0x1a, 0x01813052},
{0x1b, 0x0181405F},
{0x1d, 0x40134601},
{0x1e, 0x01441130},
{0x11, 0x18567140},
{0x20, 0x0030FFFF},
{0xff, 0xffffffff}
};
/**
* Pin Config for ALC0861.
*
*
*
*/
CODECENTRY AzaliaCodecAlc861Table[] =
{
{0x01, 0x8086C601},
{0x0B, 0x01014110},
{0x0C, 0x01813140},
{0x0D, 0x01A19941},
{0x0E, 0x411111F0},
{0x0F, 0x02214420},
{0x10, 0x02A1994E},
{0x11, 0x99330142},
{0x12, 0x01451130},
{0x1F, 0x411111F0},
{0x20, 0x411111F0},
{0x23, 0x411111F0},
{0xff, 0xffffffff}
};
/**
* Pin Config for ALC0889.
*
*
*
*/
CODECENTRY AzaliaCodecAlc889Table[] =
{
{0x11, 0x411111F0},
{0x14, 0x01014010},
{0x15, 0x01011012},
{0x16, 0x01016011},
{0x17, 0x01013014},
{0x18, 0x01A19030},
{0x19, 0x411111F0},
{0x1a, 0x411111F0},
{0x1b, 0x411111F0},
{0x1C, 0x411111F0},
{0x1d, 0x411111F0},
{0x1e, 0x01442150},
{0x1f, 0x01C42160},
{0xff, 0xffffffff}
};
/**
* Pin Config for ADI1984.
*
*
*
*/
CODECENTRY AzaliaCodecAd1984Table[] =
{
{0x11, 0x0221401F},
{0x12, 0x90170110},
{0x13, 0x511301F0},
{0x14, 0x02A15020},
{0x15, 0x50A301F0},
{0x16, 0x593301F0},
{0x17, 0x55A601F0},
{0x18, 0x55A601F0},
{0x1A, 0x91F311F0},
{0x1B, 0x014511A0},
{0x1C, 0x599301F0},
{0xff, 0xffffffff}
};
/**
* FrontPanel Config table list
*
*
*
*/
CODECENTRY FrontPanelAzaliaCodecTableList[] =
{
{0x19, 0x02A19040},
{0x1b, 0x02214020},
{0xff, 0xffffffff}
};
/**
* Current HD Audio support codec list
*
*
*
*/
CODECTBLLIST azaliaCodecTableList[] =
{
{0x010ec0880, &AzaliaCodecAlc882Table[0]},
{0x010ec0882, &AzaliaCodecAlc882Table[0]},
{0x010ec0883, &AzaliaCodecAlc882Table[0]},
{0x010ec0885, &AzaliaCodecAlc882Table[0]},
{0x010ec0889, &AzaliaCodecAlc889Table[0]},
{0x010ec0262, &AzaliaCodecAlc262Table[0]},
{0x010ec0269, &AzaliaCodecAlc269Table[0]},
{0x010ec0861, &AzaliaCodecAlc861Table[0]},
{0x011d41984, &AzaliaCodecAd1984Table[0]},
{ (UINT32) 0x0FFFFFFFF, (CODECENTRY*) (UINTN)0x0FFFFFFFF}
};
/**
* azaliaInitBeforePciEnum - Config HD Audio Before PCI emulation
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID
azaliaInitBeforePciEnum (
IN AMDSBCFG* pConfig
)
{
if ( pConfig->AzaliaController == 1 ) {
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEB, AccWidthUint8, ~BIT0, 0);
} else {
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEB, AccWidthUint8, ~BIT0, BIT0);
if ( pConfig->BuildParameters.HdAudioMsi) {
RWPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG44, AccWidthUint32 | S3_SAVE, ~BIT8, BIT8);
RWPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG60, AccWidthUint32 | S3_SAVE, ~BIT16, BIT16);
}
}
}
/**
* azaliaInitAfterPciEnum - Config HD Audio after PCI emulation
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID
azaliaInitAfterPciEnum (
IN AMDSBCFG* pConfig
)
{
UINT8 Data;
UINT8 i;
UINT8 dbEnableAzalia;
UINT8 dbPinRouting;
UINT8 dbChannelNum;
UINT8 dbTempVariable;
UINT16 dwTempVariable;
UINT32 ddBAR0;
UINT32 ddTempVariable;
dbEnableAzalia = 0;
dbChannelNum = 0;
dbTempVariable = 0;
dwTempVariable = 0;
ddBAR0 = 0;
ddTempVariable = 0;
if ( pConfig->AzaliaController == 1 ) {
return;
}
if ( pConfig->AzaliaController != 1 ) {
RWPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG04, AccWidthUint8 | S3_SAVE, ~BIT1, BIT1);
if ( pConfig->BuildParameters.AzaliaSsid != NULL ) {
RWPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.AzaliaSsid);
}
ReadPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG10, AccWidthUint32, &ddBAR0);
if ( ddBAR0 != 0 ) {
if ( ddBAR0 != 0xFFFFFFFF ) {
ddBAR0 &= ~(0x03FFF);
dbEnableAzalia = 1;
}
}
}
if ( dbEnableAzalia ) {
// Get SDIN Configuration
if ( pConfig->AZALIACONFIG.AzaliaConfig.AzaliaSdin0 == 2 ) {
RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG167, AccWidthUint8, 0, 0x3E);
RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG167, AccWidthUint8, 0, 0x00);
} else {
RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG167, AccWidthUint8, 0, 0x0);
RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG167, AccWidthUint8, 0, 0x01);
}
if ( pConfig->AZALIACONFIG.AzaliaConfig.AzaliaSdin1 == 2 ) {
RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG168, AccWidthUint8, 0, 0x3E);
RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG168, AccWidthUint8, 0, 0x00);
} else {
RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG168, AccWidthUint8, 0, 0x0);
RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG168, AccWidthUint8, 0, 0x01);
}
if ( pConfig->AZALIACONFIG.AzaliaConfig.AzaliaSdin2 == 2 ) {
RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG169, AccWidthUint8, 0, 0x3E);
RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG169, AccWidthUint8, 0, 0x00);
} else {
RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG169, AccWidthUint8, 0, 0x0);
RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG169, AccWidthUint8, 0, 0x01);
}
if ( pConfig->AZALIACONFIG.AzaliaConfig.AzaliaSdin3 == 2 ) {
RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG170, AccWidthUint8, 0, 0x3E);
RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG170, AccWidthUint8, 0, 0x00);
} else {
RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG170, AccWidthUint8, 0, 0x0);
RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG170, AccWidthUint8, 0, 0x01);
}
// INT#A Azalia resource
Data = 0x93; // Azalia APIC index
WriteIO (SB_IOMAP_REGC00, AccWidthUint8, &Data);
Data = 0x10; // IRQ16 (INTA#)
WriteIO (SB_IOMAP_REGC01, AccWidthUint8, &Data);
i = 11;
do {
ReadMEM ( ddBAR0 + SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable);
dbTempVariable |= BIT0;
WriteMEM (ddBAR0 + SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable);
SbStall (1000);
ReadMEM (ddBAR0 + SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable);
i--;
} while ((! (dbTempVariable & BIT0)) && (i > 0) );
if ( i == 0 ) {
return;
}
SbStall (1000);
ReadMEM ( ddBAR0 + SB_AZ_BAR_REG0E, AccWidthUint16, &dwTempVariable);
if ( dwTempVariable & 0x0F ) {
//atleast one azalia codec found
// ?? E0 is not real register what we expect. we have change to GPIO/and program GPIO Mux
//ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGE0, AccWidthUint8, &dbPinRouting);
dbPinRouting = pConfig->AZALIACONFIG.AzaliaSdinPin;
do {
if ( ( ! (dbPinRouting & BIT0) ) && (dbPinRouting & BIT1) ) {
// dbChannelNum = 3;
configureAzaliaPinCmd (pConfig, ddBAR0, dbChannelNum);
}
dbPinRouting >>= 2;
dbChannelNum++;
} while ( dbChannelNum != 4 );
} else {
//No Azalia codec found
if ( pConfig->AzaliaController != 2 ) {
dbEnableAzalia = 0; //set flag to disable Azalia
}
}
}
if ( dbEnableAzalia ) {
//redo clear reset
do {
dwTempVariable = 0;
WriteMEM ( ddBAR0 + SB_AZ_BAR_REG0C, AccWidthUint16 | S3_SAVE, &dwTempVariable);
ReadMEM (ddBAR0 + SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable);
dbTempVariable &= ~(BIT0);
WriteMEM (ddBAR0 + SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable);
ReadMEM (ddBAR0 + SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable);
} while ( dbTempVariable & BIT0 );
if ( pConfig->AzaliaSnoop == 1 ) {
RWPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG42, AccWidthUint8 | S3_SAVE, 0xFF, BIT1 + BIT0);
}
} else {
//disable Azalia controller
RWPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG04, AccWidthUint16 | S3_SAVE, 0, 0);
// RWPMIO (SB_PMIO_REG59, AccWidthUint8 | S3_SAVE, ~BIT3, 0);
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEB, AccWidthUint8, ~BIT0, 0);
// RWPCI ((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REGFC, AccWidthUint8 | S3_SAVE, 0, 0x55);
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEB, AccWidthUint8, ~BIT0, 0);
}
}
/**
* configureAzaliaPinCmd - Configuration HD Audio PIN Command
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
* @param[in] ddBAR0 HD Audio BAR0 base address.
* @param[in] dbChannelNum Channel Number.
*
*/
VOID
configureAzaliaPinCmd (
IN AMDSBCFG* pConfig,
IN UINT32 ddBAR0,
IN UINT8 dbChannelNum
)
{
UINT32 ddTempVariable;
UINT32 ddChannelNum;
CODECTBLLIST* ptempAzaliaOemCodecTablePtr;
CODECENTRY* tempAzaliaCodecEntryPtr;
if ( (pConfig->AzaliaPinCfg) != 1 ) {
return;
}
ddChannelNum = dbChannelNum << 28;
ddTempVariable = 0xF0000;
ddTempVariable |= ddChannelNum;
WriteMEM (ddBAR0 + SB_AZ_BAR_REG60, AccWidthUint32 | S3_SAVE, &ddTempVariable);
SbStall (600);
ReadMEM (ddBAR0 + SB_AZ_BAR_REG64, AccWidthUint32 | S3_SAVE, &ddTempVariable);
if ( ((pConfig->AZOEMTBL.pAzaliaOemCodecTablePtr) == NULL) || ((pConfig->AZOEMTBL.pAzaliaOemCodecTablePtr) == ((CODECTBLLIST*) (UINTN)0xFFFFFFFF))) {
ptempAzaliaOemCodecTablePtr = (CODECTBLLIST*) FIXUP_PTR (&azaliaCodecTableList[0]);
} else {
ptempAzaliaOemCodecTablePtr = (CODECTBLLIST*) pConfig->AZOEMTBL.pAzaliaOemCodecTablePtr;
}
while ( ptempAzaliaOemCodecTablePtr->CodecID != 0xFFFFFFFF ) {
if ( ptempAzaliaOemCodecTablePtr->CodecID == ddTempVariable ) {
break;
} else {
++ptempAzaliaOemCodecTablePtr;
}
}
if ( ptempAzaliaOemCodecTablePtr->CodecID != 0xFFFFFFFF ) {
tempAzaliaCodecEntryPtr = (CODECENTRY*) ptempAzaliaOemCodecTablePtr->CodecTablePtr;
if ( ((pConfig->AZOEMTBL.pAzaliaOemCodecTablePtr) == NULL) || ((pConfig->AZOEMTBL.pAzaliaOemCodecTablePtr) == ((CODECTBLLIST*) (UINTN)0xFFFFFFFF)) ) {
tempAzaliaCodecEntryPtr = (CODECENTRY*) FIXUP_PTR (tempAzaliaCodecEntryPtr);
}
configureAzaliaSetConfigD4Dword (tempAzaliaCodecEntryPtr, ddChannelNum, ddBAR0);
if ( pConfig->AzaliaFrontPanel != 1 ) {
if ( (pConfig->AzaliaFrontPanel == 2) || (pConfig->FrontPanelDetected == 1) ) {
if ( ((pConfig->AZOEMFPTBL.pAzaliaOemFpCodecTablePtr) == NULL) || ((pConfig->AZOEMFPTBL.pAzaliaOemFpCodecTablePtr) == (VOID*) (UINTN)0xFFFFFFFF) ) {
tempAzaliaCodecEntryPtr = (CODECENTRY*) FIXUP_PTR (&FrontPanelAzaliaCodecTableList[0]);
} else {
tempAzaliaCodecEntryPtr = (CODECENTRY*) pConfig->AZOEMFPTBL.pAzaliaOemFpCodecTablePtr;
}
configureAzaliaSetConfigD4Dword (tempAzaliaCodecEntryPtr, ddChannelNum, ddBAR0);
}
}
}
}
/**
* configureAzaliaSetConfigD4Dword - Configuration HD Audio Codec table
*
*
* @param[in] tempAzaliaCodecEntryPtr HD Audio Codec table structure pointer.
* @param[in] ddChannelNum HD Audio Channel Number.
* @param[in] ddBAR0 HD Audio BAR0 base address.
*
*/
VOID
configureAzaliaSetConfigD4Dword (
IN CODECENTRY* tempAzaliaCodecEntryPtr,
IN UINT32 ddChannelNum,
IN UINT32 ddBAR0
)
{
UINT8 dbtemp1;
UINT8 dbtemp2;
UINT8 i;
UINT32 ddtemp;
UINT32 ddtemp2;
ddtemp = 0;
ddtemp2 = 0;
while ( (tempAzaliaCodecEntryPtr->Nid) != 0xFF ) {
dbtemp1 = 0x20;
if ( (tempAzaliaCodecEntryPtr->Nid) == 0x1 ) {
dbtemp1 = 0x24;
}
ddtemp = tempAzaliaCodecEntryPtr->Nid;
ddtemp &= 0xff;
ddtemp <<= 20;
ddtemp |= ddChannelNum;
ddtemp |= (0x700 << 8);
for ( i = 4; i > 0; i-- ) {
do {
ReadMEM (ddBAR0 + SB_AZ_BAR_REG68, AccWidthUint32, &ddtemp2);
} while ( ddtemp2 & BIT0 );
dbtemp2 = (UINT8) (( (tempAzaliaCodecEntryPtr->Byte40) >> ((4 - i) * 8 ) ) & 0xff);
ddtemp = (ddtemp & 0xFFFF0000) + ((dbtemp1 - i) << 8) + dbtemp2;
WriteMEM (ddBAR0 + SB_AZ_BAR_REG60, AccWidthUint32 | S3_SAVE, &ddtemp);
SbStall (60);
}
++tempAzaliaCodecEntryPtr;
}
}

247
src/vendorcode/amd/cimx/sb800/DISPATCHER.c Normal file
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/**
* @file
*
* Function dispatcher.
*
*
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: CIMx-SB
* @e sub-project:
* @e \$Revision:$ @e \$Date:$
*
*/
/*
*****************************************************************************
*
* This file is part of the coreboot project.
*
* Copyright (C) 2010 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
* ***************************************************************************
*
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "SBPLATFORM.h"
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
//
// Declaration of local functions
//
VOID saveConfigPointer (IN AMDSBCFG* pConfig);
VOID* VerifyImage (IN UINT64 Signature, IN VOID* ImagePtr);
VOID* LocateImage (IN UINT64 Signature);
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/**
* AmdSbDispatcher - Dispatch Southbridge function
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
AGESA_STATUS
AmdSbDispatcher (
IN VOID *pConfig
)
{
AGESA_STATUS Status;
#ifdef B1_IMAGE
VOID *pAltImagePtr;
CIM_IMAGE_ENTRY AltImageEntry;
#endif
UINT64 tdValue;
tdValue = 0x32314130384253ULL;
#ifdef B1_IMAGE
pAltImagePtr = NULL;
#endif
Status = AGESA_UNSUPPORTED;
#ifdef B1_IMAGE
if ((UINT32) (UINTN) (((AMD_CONFIG_PARAMS*)pConfig)->AltImageBasePtr) != 0xffffffff ) {
if ( ((AMD_CONFIG_PARAMS*)pConfig)->AltImageBasePtr ) {
pAltImagePtr = VerifyImage ( tdValue, (VOID*) (UINTN) ((AMD_CONFIG_PARAMS*)pConfig)->AltImageBasePtr);
}
if ( pAltImagePtr == NULL ) {
pAltImagePtr = LocateImage ( tdValue );
}
if ( pAltImagePtr != NULL ) {
((AMD_CONFIG_PARAMS*)pConfig)->ImageBasePtr = (UINT32) (UINTN) pAltImagePtr;
AltImageEntry = (CIM_IMAGE_ENTRY) (UINTN) ((UINT32) (UINTN) pAltImagePtr + (UINT32) (((AMD_IMAGE_HEADER*) (UINTN) pAltImagePtr)->EntryPointAddress));
(*AltImageEntry) (pConfig);
return Status;
}
}
#endif
saveConfigPointer (pConfig);
if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_POWERON_INIT ) {
sbPowerOnInit ((AMDSBCFG*) pConfig);
}
#ifndef B1_IMAGE
if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_BEFORE_PCI_INIT ) {
sbBeforePciInit ((AMDSBCFG*)pConfig);
}
if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_AFTER_PCI_INIT ) {
sbAfterPciInit ((AMDSBCFG*)pConfig);
}
if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_MID_POST_INIT ) {
sbMidPostInit ((AMDSBCFG*)pConfig);
}
if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_LATE_POST_INIT ) {
sbLatePost ((AMDSBCFG*)pConfig);
}
if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_BEFORE_PCI_RESTORE_INIT ) {
sbBeforePciRestoreInit ((AMDSBCFG*)pConfig);
}
if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_AFTER_PCI_RESTORE_INIT ) {
sbAfterPciRestoreInit ((AMDSBCFG*)pConfig);
}
if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_SMM_SERVICE ) {
sbSmmService ((AMDSBCFG*)pConfig);
}
if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_SMM_ACPION ) {
sbSmmAcpiOn ((AMDSBCFG*)pConfig);
}
if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_EC_FANCONTROL ) {
sbECfancontrolservice((AMDSBCFG*)pConfig);;
}
#endif
return Status;
}
/**
* LocateImage - Locate Southbridge CIMx module
*
*
*
* @param[in] Signature Southbridge CIMx image signature.
*
*/
VOID*
LocateImage (
IN UINT64 Signature
)
{
VOID *Result;
UINT32 ImagePtr;
ImagePtr = 0xffffffff - (IMAGE_ALIGN - 1);
while ( ImagePtr >= (0xfffffff - (NUM_IMAGE_LOCATION * IMAGE_ALIGN - 1)) ) {
#ifdef x64
12346789
#else
Result = VerifyImage (Signature, (VOID*) ImagePtr);
#endif
if ( Result != NULL ) {
return Result;
}
ImagePtr -= IMAGE_ALIGN;
}
return NULL;
}
/**
* VerifyImage - Verify Southbridge CIMx module
*
*
* @param[in] Signature Southbridge CIMx image signature.
* @param[in] ImagePtr Southbridge CIMx image address.
*
*/
VOID*
VerifyImage (
IN UINT64 Signature,
IN VOID* ImagePtr
)
{
UINT16 *TempImagePtr;
UINT16 Sum;
UINT32 i;
Sum = 0;
//if ( (*((UINT32*)ImagePtr) == 'DMA$' && ((CIMFILEHEADER*)ImagePtr)->CreatorID == Signature) ) { //gcc multi-character character constant warning
if ( (*((UINT32*)ImagePtr) == 0x444d4124 && ((CIMFILEHEADER*)ImagePtr)->CreatorID == Signature) ) {//'DMA$'
//GetImage Image size
TempImagePtr = (UINT16*)ImagePtr;
for ( i = 0; i < (((CIMFILEHEADER*)ImagePtr)->ImageSize); i += 2 ) {
Sum = Sum + *TempImagePtr;
TempImagePtr++;
}
if ( Sum == 0 ) {
return ImagePtr;
}
}
return NULL;
}
/**
* saveConfigPointer - Verify Southbridge CIMx module
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID
saveConfigPointer (
IN AMDSBCFG* pConfig
)
{
UINT8 dbReg;
UINT8 i;
UINT32 ddValue;
ddValue = (UINT32) (UINTN)pConfig;
dbReg = SB_ECMOS_REG08;
for ( i = 0; i <= 3; i++ ) {
WriteIO (SB_IOMAP_REG72, AccWidthUint8, &dbReg);
WriteIO (SB_IOMAP_REG73, AccWidthUint8, (UINT8*)&ddValue);
ddValue = (ddValue >> 8);
dbReg++;
}
}

121
src/vendorcode/amd/cimx/sb800/EC.c Normal file
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/**
* @file
*
* Config Southbridge EC Controller
*
* Init EC features.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: CIMx-SB
* @e sub-project:
* @e \$Revision:$ @e \$Date:$
*
*/
/*
*****************************************************************************
*
* This file is part of the coreboot project.
*
* Copyright (C) 2010 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
* ***************************************************************************
*
*/
#include "SBPLATFORM.h"
#ifndef NO_EC_SUPPORT
/**
* Config EC controller during power-on
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID
ecPowerOnInit (
IN AMDSBCFG* pConfig
)
{
//Enable config mode
EnterEcConfig ();
//Do settings for mailbox - logical device 0x09
RWEC8 (0x07, 0x00, 0x09); //switch to device 9 (Mailbox)
RWEC8 (0x60, 0x00, (MailBoxPort >> 8)); //set MSB of Mailbox port
RWEC8 (0x61, 0x00, (MailBoxPort & 0xFF)); //set LSB of Mailbox port
RWEC8 (0x30, 0x00, 0x01); //;Enable Mailbox Registers Interface, bit0=1
if ( pConfig->BuildParameters.EcKbd == ENABLED) {
//Enable KBRST#, IRQ1 & IRQ12, GateA20 Function signal from IMC
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD6, AccWidthUint8, ~BIT8, BIT0 + BIT1 + BIT2 + BIT3);
//Disable LPC Decoding of port 60/64
RWPCI (((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG47), AccWidthUint8 | S3_SAVE, ~BIT5, 0);
//Enable logical device 0x07 (Keyboard controller)
RWEC8 (0x07, 0x00, 0x07);
RWEC8 (0x30, 0x00, 0x01);
}
if ( pConfig->BuildParameters.EcChannel0 == ENABLED) {
//Logical device 0x03
RWEC8 (0x07, 0x00, 0x03);
RWEC8 (0x60, 0x00, 0x00);
RWEC8 (0x61, 0x00, 0x62);
RWEC8 (0x30, 0x00, 0x01); //;Enable Device 8
}
//Enable EC (IMC) to generate SMI to BIOS
RWMEM (ACPI_MMIO_BASE + SMI_BASE + SB_SMI_REGB3, AccWidthUint8, ~BIT6, BIT6);
ExitEcConfig ();
}
/**
* Config EC controller before PCI emulation
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID
ecInitBeforePciEnum (
IN AMDSBCFG* pConfig
)
{
AMDSBCFG* pTmp; // dummy code
pTmp = pConfig;
}
/**
* Prepare EC controller to boot to OS.
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID
ecInitLatePost (
IN AMDSBCFG* pConfig
)
{
AMDSBCFG* pTmp; // dummy code
pTmp = pConfig;
}
#endif

146
src/vendorcode/amd/cimx/sb800/ECLIB.c Normal file
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/**
* @file
*
* Southbridge EC IO access common routine
*
*/
/*
*****************************************************************************
*
* This file is part of the coreboot project.
*
* Copyright (C) 2010 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
* ***************************************************************************
*
*/
#include "SBPLATFORM.h"
// #ifndef NO_EC_SUPPORT
/*----------------------------------------------------------------------------------------*/
/**
* EnterEcConfig - Force EC into Config mode
*
*
*
*
*/
VOID
EnterEcConfig (
)
{
UINT16 dwEcIndexPort;
ReadPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4, AccWidthUint16 | S3_SAVE, &dwEcIndexPort);
dwEcIndexPort &= ~(BIT0);
RWIO (dwEcIndexPort, AccWidthUint8, 0x00, 0x5A);
}
/*----------------------------------------------------------------------------------------*/
/**
* ExitEcConfig - Force EC exit Config mode
*
*
*
*
*/
VOID
ExitEcConfig (
)
{
UINT16 dwEcIndexPort;
ReadPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4, AccWidthUint16 | S3_SAVE, &dwEcIndexPort);
dwEcIndexPort &= ~(BIT0);
RWIO (dwEcIndexPort, AccWidthUint8, 0x00, 0xA5);
}
/*----------------------------------------------------------------------------------------*/
/**
* ReadEC8 - Read EC register data
*
*
*
* @param[in] Address - EC Register Offset Value
* @param[in] Value - Read Data Buffer
*
*/
VOID
ReadEC8 (
IN UINT8 Address,
IN UINT8* Value
)
{
UINT16 dwEcIndexPort;
ReadPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4, AccWidthUint16 | S3_SAVE, &dwEcIndexPort);
dwEcIndexPort &= ~(BIT0);
WriteIO (dwEcIndexPort, AccWidthUint8, &Address);
ReadIO (dwEcIndexPort + 1, AccWidthUint8, Value);
}
/*----------------------------------------------------------------------------------------*/
/**
* WriteEC8 - Write date into EC register
*
*
*
* @param[in] Address - EC Register Offset Value
* @param[in] Value - Write Data Buffer
*
*/
VOID
WriteEC8 (
IN UINT8 Address,
IN UINT8* Value
)
{
UINT16 dwEcIndexPort;
ReadPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4, AccWidthUint16 | S3_SAVE, &dwEcIndexPort);
dwEcIndexPort &= ~(BIT0);
WriteIO (dwEcIndexPort, AccWidthUint8, &Address);
WriteIO (dwEcIndexPort + 1, AccWidthUint8, Value);
}
/*----------------------------------------------------------------------------------------*/
/**
* RWEC8 - Read/Write EC register
*
*
*
* @param[in] Address - EC Register Offset Value
* @param[in] AndMask - Data And Mask 8 bits
* @param[in] OrMask - Data OR Mask 8 bits
*
*/
VOID
RWEC8 (
IN UINT8 Address,
IN UINT8 AndMask,
IN UINT8 OrMask
)
{
UINT8 Result;
ReadEC8 (Address, &Result);
Result = (Result & AndMask) | OrMask;
WriteEC8 (Address, &Result);
}
// #endif

60
src/vendorcode/amd/cimx/sb800/ECfan.h Normal file
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/*
*****************************************************************************
*
* This file is part of the coreboot project.
*
* Copyright (C) 2010 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
* ***************************************************************************
*
*/
VOID WriteECmsg (IN UINT8 Address, IN UINT8 OpFlag, IN VOID* Value);
VOID WaitForEcLDN9MailboxCmdAck (VOID);
VOID ReadECmsg (IN UINT8 Address, IN UINT8 OpFlag, OUT VOID* Value);
// IMC Message Register Software Interface
#define CPU_MISC_BUS_DEV_FUN ((0x18 << 3) + 3)
#define MSG_SYS_TO_IMC 0x80
#define Fun_80 0x80
#define Fun_81 0x81
#define Fun_82 0x82
#define Fun_83 0x83
#define Fun_84 0x84
#define Fun_85 0x85
#define Fun_86 0x86
#define Fun_87 0x87
#define Fun_88 0x88
#define Fun_89 0x89
#define Fun_90 0x90
#define MSG_IMC_TO_SYS 0x81
#define MSG_REG0 0x82
#define MSG_REG1 0x83
#define MSG_REG2 0x84
#define MSG_REG3 0x85
#define MSG_REG4 0x86
#define MSG_REG5 0x87
#define MSG_REG6 0x88
#define MSG_REG7 0x89
#define MSG_REG8 0x8A
#define MSG_REG9 0x8B
#define MSG_REGA 0x8C
#define MSG_REGB 0x8D
#define MSG_REGC 0x8E
#define MSG_REGD 0x8F

87
src/vendorcode/amd/cimx/sb800/ECfanLIB.c Normal file
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/**
* @file
*
* Southbridge EC IO access common routine
*
*/
/*
*****************************************************************************
*
* This file is part of the coreboot project.
*
* Copyright (C) 2010 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
* ***************************************************************************
*
*/
#include "SBPLATFORM.h"
#include "ECfan.h"
VOID
ReadECmsg (
IN UINT8 Address,
IN UINT8 OpFlag,
OUT VOID* Value
)
{
UINT8 i;
OpFlag = OpFlag & 0x7f;
if (OpFlag == 0x02) OpFlag = 0x03;
for (i = 0; i <= OpFlag; i++) {
WriteIO(MailBoxPort, AccWidthUint8, &Address); // EC_LDN9_MAILBOX_BASE_ADDRESS
Address++;
ReadIO(MailBoxPort + 1, AccWidthUint8, (UINT8 *)Value+i); // EC_LDN9_MAILBOX_BASE_ADDRESS
}
}
VOID
WriteECmsg (
IN UINT8 Address,
IN UINT8 OpFlag,
IN VOID* Value
)
{
UINT8 i;
OpFlag = OpFlag & 0x7f;
if (OpFlag == 0x02) OpFlag = 0x03;
for (i = 0; i <= OpFlag; i++) {
WriteIO(MailBoxPort, AccWidthUint8, &Address); // EC_LDN9_MAILBOX_BASE_ADDRESS
Address++;
WriteIO(MailBoxPort + 1, AccWidthUint8, (UINT8 *)Value+i); // EC_LDN9_MAILBOX_BASE_ADDRESS
}
}
VOID
WaitForEcLDN9MailboxCmdAck (
VOID
)
{
UINT8 Msgdata;
UINT16 Delaytime;
Msgdata = 0;
for (Delaytime = 0; Delaytime <= 500; Delaytime++) {
ReadECmsg (MSG_REG0, AccWidthUint8, &Msgdata);
if ( Msgdata == 0xfa) {
break;
}
SbStall (1000); // Wait for 1ms
}
}

195
src/vendorcode/amd/cimx/sb800/ECfanc.c Normal file
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/*
*****************************************************************************
*
* This file is part of the coreboot project.
*
* Copyright (C) 2010 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
* ***************************************************************************
*
*/
#include "SBPLATFORM.h"
#include "ECfan.h"
/**
* Table for Function Number
*
*
*
*
*/
UINT8 FunctionNumber[] =
{
Fun_81,
Fun_83,
Fun_85,
Fun_89,
};
/**
* Table for Max Thermal Zone
*
*
*
*
*/
UINT8 MaxZone[] =
{
4,
4,
4,
4,
};
/**
* Table for Max Register
*
*
*
*
*/
UINT8 MaxRegister[] =
{
MSG_REG9,
MSG_REGB,
MSG_REG9,
MSG_REGA,
};
/*-------------------------------------------------------------------------------
;Procedure: IsZoneFuncEnable
;
;Description: This routine will check every zone support function with BitMap from user define
;
;
;Exit: None
;
;Modified: None
;
;-----------------------------------------------------------------------------
*/
BOOLEAN
IsZoneFuncEnable (
UINT16 Flag,
UINT8 func,
UINT8 Zone
)
{
return (BOOLEAN)(((Flag >> (func *4)) & 0xF) & ((UINT8 )1 << Zone));
}
/*-------------------------------------------------------------------------------
;Procedure: sbECfancontrolservice
;
;Description: This routine service EC fan policy
;
;
;Exit: None
;
;Modified: None
;
;-----------------------------------------------------------------------------
*/
VOID
sbECfancontrolservice (
IN AMDSBCFG* pConfig
)
{
UINT8 ZoneNum;
UINT8 FunNum;
UINT8 RegNum;
UINT8 * CurPoint;
UINT8 FunIndex;
BOOLEAN IsSendEcMsg;
CurPoint = &pConfig->Pecstruct.MSGFun81zone0MSGREG0 + MaxZone[0] * (MaxRegister[0] - MSG_REG0 + 1);
for ( FunIndex = 1; FunIndex <= 3; FunIndex++ ) {
FunNum = FunctionNumber[FunIndex];
for ( ZoneNum = 0; ZoneNum < MaxZone[FunIndex]; ZoneNum++ ) {
IsSendEcMsg = IsZoneFuncEnable (pConfig->Pecstruct.IMCFUNSupportBitMap, FunIndex, ZoneNum);
for ( RegNum = MSG_REG0; RegNum <= MaxRegister[FunIndex]; RegNum++ ) {
if (IsSendEcMsg) {
WriteECmsg (RegNum, AccWidthUint8, CurPoint); //
}
CurPoint += 1;
}
if (IsSendEcMsg) {
WriteECmsg (MSG_SYS_TO_IMC, AccWidthUint8, &FunNum); // function number
WaitForEcLDN9MailboxCmdAck ();
}
}
}
CurPoint = &pConfig->Pecstruct.MSGFun81zone0MSGREG0;
for ( FunIndex = 0; FunIndex <= 0; FunIndex++ ) {
FunNum = FunctionNumber[FunIndex];
for ( ZoneNum = 0; ZoneNum < MaxZone[FunIndex]; ZoneNum++ ) {
IsSendEcMsg = IsZoneFuncEnable (pConfig->Pecstruct.IMCFUNSupportBitMap, FunIndex, ZoneNum);
for ( RegNum = MSG_REG0; RegNum <= MaxRegister[FunIndex]; RegNum++ ) {
if (IsSendEcMsg) {
WriteECmsg (RegNum, AccWidthUint8, CurPoint); //
}
CurPoint += 1;
}
if (IsSendEcMsg) {
WriteECmsg (MSG_SYS_TO_IMC, AccWidthUint8, &FunNum); // function number
WaitForEcLDN9MailboxCmdAck ();
}
}
}
}
/*-------------------------------------------------------------------------------
;Procedure: SBIMCFanInitializeS3
;
;Description: This routine initialize IMC fan when S3 resume
;
;
;Exit: None
;
;Modified: None
;
;-----------------------------------------------------------------------------
*/
VOID
SBIMCFanInitializeS3 (VOID)
{
UINT8 dbPortStatus,Value80,Value82,Value83,Value84;
getChipSysMode (&dbPortStatus);
if ((dbPortStatus & ChipSysEcEnable) != 0) {
Value80 = 0x98;
Value82 = 0x00;
Value83 = 0x02;
Value84 = 0x00;
// Clear MSG_REG0 to receive acknowledge byte
WriteECmsg (MSG_REG0, AccWidthUint8, &Value82);
// Set MSG_REG1
// 0x02 - Notify IMC that the system is waken from any sleep state
WriteECmsg (MSG_REG1, AccWidthUint8, &Value83);
// Set timeout counter value to 00 which disables watchdog timer
WriteECmsg (MSG_REG2, AccWidthUint8, &Value84);
// Write mailbox function number to kick off the command
// 0x98 - IMC System Sleep and Wake Services
WriteECmsg (MSG_SYS_TO_IMC, AccWidthUint8, &Value80);
// Read acknowledge byte to make sure function is executed properly
WaitForEcLDN9MailboxCmdAck ();
}
}

135
src/vendorcode/amd/cimx/sb800/GEC.c Normal file
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/**
* @file
*
* Config Southbridge GEC controller
*
* Init GEC features.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: CIMx-SB
* @e sub-project:
* @e \$Revision:$ @e \$Date:$
*
*/
/*
*****************************************************************************
*
* This file is part of the coreboot project.
*
* Copyright (C) 2010 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
* ***************************************************************************
*
*/
#include "SBPLATFORM.h"
/**
* gecInitBeforePciEnum - Config GEC controller before PCI emulation
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID
gecInitBeforePciEnum (
IN AMDSBCFG* pConfig
)
{
UINT8 cimSBGecDebugBus;
UINT8 cimSBGecPwr;
cimSBGecDebugBus = (UINT8) pConfig->SBGecDebugBus;
cimSBGecPwr = (UINT8) pConfig->SBGecPwr;
#if SB_CIMx_PARAMETER == 0
cimSBGecDebugBus = cimSBGecDebugBusDefault;
cimSBGecPwr = cimSBGecPwrDefault;
#endif
if ( pConfig->GecConfig == 0) {
// GEC Enabled
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF6, AccWidthUint8, ~BIT0, 0x00);
RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GEVENT_REG11, AccWidthUint8, 0, 0x00);
RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GEVENT_REG21, AccWidthUint8, 0, 0x01);
RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG166, AccWidthUint8, 0, 0x01);
//RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG181, AccWidthUint8, 0, 0x01);
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF8, AccWidthUint8, ~(BIT5 + BIT6), (UINT8) ((cimSBGecPwr) << 5));
} else {
// GEC Disabled
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF6, AccWidthUint8, ~BIT0, BIT0);
return; //return if GEC controller is disabled.
}
if ( cimSBGecDebugBus == 1) {
// GEC Debug Bus Enabled
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF6, AccWidthUint8, ~BIT3, BIT3);
} else {
// GEC Debug Bus Disabled
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF6, AccWidthUint8, ~BIT3, 0x00);
}
}
/**
* gecInitAfterPciEnum - Config GEC controller after PCI emulation
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID
gecInitAfterPciEnum (
IN AMDSBCFG* pConfig
)
{
VOID* GecRomAddress;
VOID* GecShadowRomAddress;
UINT32 ddTemp;
UINT8 dbVar;
UINT8 dbTemp;
if ( pConfig->GecConfig == 0) {
dbVar = 0;
ReadPCI ((GEC_BUS_DEV_FUN << 16) + SB_GEC_REG04, AccWidthUint8, &dbVar);
dbTemp = 0x07;
WritePCI ((GEC_BUS_DEV_FUN << 16) + SB_GEC_REG04, AccWidthUint8, &dbTemp);
if ( !pConfig->DYNAMICGECROM.DynamicGecRomAddress_Ptr == NULL ) {
GecRomAddress = pConfig->DYNAMICGECROM.DynamicGecRomAddress_Ptr;
GecShadowRomAddress = (VOID*) (UINTN) pConfig->BuildParameters.GecShadowRomBase;
AmdSbCopyMem (GecShadowRomAddress, GecRomAddress, 0x100);
ReadPCI ((GEC_BUS_DEV_FUN << 16) + SB_GEC_REG10, AccWidthUint32, &ddTemp);
ddTemp = ddTemp & 0xFFFFFFF0;
RWMEM (ddTemp + 0x6804, AccWidthUint32, 0, BIT0 + BIT29);
}
WritePCI ((GEC_BUS_DEV_FUN << 16) + SB_GEC_REG04, AccWidthUint8, &dbVar);
}
}
/**
* gecInitLatePost - Prepare GEC controller to boot to OS.
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID
gecInitLatePost (
IN AMDSBCFG* pConfig
)
{
if ( !pConfig->GecConfig == 0) {
return; //return if GEC controller is disabled.
}
}

887
src/vendorcode/amd/cimx/sb800/Gpp.c Normal file
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/**
* @file
*
* Config Southbridge GPP controller
*
* Init GPP features.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: CIMx-SB
* @e sub-project
* @e \$Revision:$ @e \$Date:$
*
*/
/*
*****************************************************************************
*
* This file is part of the coreboot project.
*
* Copyright (C) 2010 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
* ***************************************************************************
*
*/
#include "SBPLATFORM.h"
/**
* PCIE_CAP_ID - PCIe Cap ID
*
*/
#define PCIE_CAP_ID 0x10
//
// Declaration of local functions
//
/**
* PreInitGppLink - Enable GPP link training.
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID PreInitGppLink (IN AMDSBCFG* pConfig);
UINT8 CheckGppLinkStatus (IN AMDSBCFG* pConfig);
VOID AfterGppLinkInit (IN AMDSBCFG* pConfig);
VOID sbGppForceGen2 (IN UINT32 portId );
VOID sbGppForceGen1 (IN UINT32 portId );
VOID sbGppDisableUnusedPadMap (IN AMDSBCFG* pConfig );
VOID sbGppSetAspm (IN UINT32 pciAddress, IN UINT8 LxState);
UINT8 sbFindPciCap (IN UINT32 pciAddress, IN UINT8 targetCapId);
//
// Declaration of external functions
//
//
//-----------------------------------------------------------------------------------
// Early SB800 GPP initialization sequence:
//
// 1) Set port enable bit fields by current GPP link configuration mode
// 2) Deassert GPP reset and pull EP out of reset - Clear GPP_RESET (abcfg:0xC0[8] = 0)
// 3) Loop polling for the link status of all ports
// 4) Misc operations after link training:
// - (optional) Detect GFX device
// - Hide empty GPP configuration spaces (Disable empty GPP ports)
// - (optional) Power down unused GPP ports
// - (optional) Configure PCIE_P2P_Int_Map (abcfg:0xC4[7:0])
// 5) GPP init completed
//
//
// *) Gen2 vs Gen1
// Gen2 mode Gen1 mode
// ---------------------------------------------------------------
// STRAP_PHY_PLL_CLKF[6:0] 7'h32 7'h19
// STRAP_BIF_GEN2_EN 1 0
//
// PCIE_PHY_PLL clock locks @ 5GHz
//
//
/**
* GPP early programming and link training. On exit all populated EPs should be fully operational.
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID
sbPcieGppEarlyInit (
IN AMDSBCFG* pConfig
)
{
UINT8 TogglePort;
UINT8 portNum;
UINT32 reg32Value;
UINT8 retryCount;
UINT8 cimGppMemWrImprove;
UINT8 cimGppLaneReversal;
UINT8 cimAlinkPhyPllPowerDown;
cimGppMemWrImprove = pConfig->GppMemWrImprove;
cimGppLaneReversal = (UINT8) pConfig->GppLaneReversal;
cimAlinkPhyPllPowerDown = (UINT8) pConfig->AlinkPhyPllPowerDown;
#if SB_CIMx_PARAMETER == 0
cimGppMemWrImprove = cimGppMemWrImproveDefault;
cimGppLaneReversal = cimGppLaneReversalDefault;
cimAlinkPhyPllPowerDown = cimAlinkPhyPllPowerDownDefault;
#endif
//
// Configure NB-SB link PCIE PHY PLL power down for L1
//
if ( cimAlinkPhyPllPowerDown == TRUE ) {
UINT32 abValue;
// Set PCIE_P_CNTL in Alink PCIEIND space
writeAlink (SB_AX_INDXC_REG30 | (UINT32) (AXINDC << 29), 0x40);
abValue = readAlink (SB_AX_DATAC_REG34 | (UINT32) (AXINDC << 29));
abValue |= BIT12 + BIT3 + BIT0;
abValue &= ~(BIT9 + BIT4);
writeAlink (SB_AX_DATAC_REG34 | (UINT32) (AXINDC << 29), abValue);
rwAlink (SB_AX_INDXC_REG02 | (UINT32) (AXINDC << 29), ~BIT8, (BIT8));
}
//
// Set ABCFG 0x031C[0] = 1 enable the lane reversal support.
//
reg32Value = readAlink (SB_ABCFG_REG31C | (UINT32) (ABCFG << 29));
if ( cimGppLaneReversal ) {
writeAlink (SB_ABCFG_REG31C | (UINT32) (ABCFG << 29), reg32Value | BIT0);
} else {
writeAlink (SB_ABCFG_REG31C | (UINT32) (ABCFG << 29), reg32Value | 0x00);
}
//
// Set abcfg:0x90[20] = 1 to enable GPP bridge multi-function
//
reg32Value = readAlink (SB_ABCFG_REG90 | (UINT32) (ABCFG << 29));
writeAlink (SB_ABCFG_REG90 | (UINT32) (ABCFG << 29), reg32Value | BIT20);
//
// Initialize and configure GPP
//
if (pConfig->GppFunctionEnable) {
// PreInit - Enable GPP link training
PreInitGppLink (pConfig);
//
// GPP Upstream Memory Write Arbitration Enhancement ABCFG 0x54[26] = 1
// GPP Memory Write Max Payload Improvement RCINDC_Reg 0x10[12:10] = 0x4
//
if ( cimGppMemWrImprove == TRUE ) {
rwAlink (SB_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~BIT26, (BIT26));
rwAlink (SB_RCINDXC_REG10 | (UINT32) (RCINDXC << 29), ~(BIT12 + BIT11 + BIT10), (BIT12));
}
if ( pConfig->S3Resume ) {
for ( portNum = 0; portNum < MAX_GPP_PORTS; portNum++ ) {
reg32Value = readAlink ((SB_ABCFG_REG340 + portNum * 4) | (UINT32) (ABCFG << 29));
writeAlink ((SB_ABCFG_REG340 + portNum * 4) | (UINT32) (ABCFG << 29), reg32Value & ~BIT21);
}
}
//
// a) Loop polling regA5 -> LcState (timeout ~100ms);
// b) if (LcState[5:0] == 0x10), training successful, go to g);
// c) if any of (LcState[13:8], [21:16], [29:24]) == 0x29 or 0x2A:
// d) Clear De-emphasis bit for relevant ports;
// e) Toggle GPP reset signal (via OEM callback);
// f) go back to a);
// g) exit;
//
for (retryCount = 0; retryCount < MAX_GPP_RESETS; retryCount++) {
// Polling each GPP port for link status
TogglePort = CheckGppLinkStatus (pConfig);
if (TogglePort == 0) {
break;
} else {
// Check failure port and clear STRAP_BIF_DE_EMPHASIS_SEL_x_GPP bit (abcfg:0x34[0, 4, 8, C][21]=0)
for ( portNum = 0; portNum < MAX_GPP_PORTS; portNum++ ) {
if (TogglePort & (1 << portNum)) {
reg32Value = readAlink ((SB_ABCFG_REG340 + portNum * 4) | (UINT32) (ABCFG << 29));
writeAlink ((SB_ABCFG_REG340 + portNum * 4) | (UINT32) (ABCFG << 29), reg32Value & ~BIT21);
}
sbGppForceGen1 (portNum);
}
// Toggle GPP reset (Note this affects all SB800 GPP ports)
CallBackToOEM (CB_SBGPP_RESET_ASSERT, (UINT32)TogglePort, pConfig);
SbStall (500);
CallBackToOEM (CB_SBGPP_RESET_DEASSERT, (UINT32)TogglePort, pConfig);
}
};
// Misc operations after link training
AfterGppLinkInit (pConfig);
} else {
// RPR 5.11 Power Saving With GPP Disable
// ABCFG 0xC0[8] = 0x0
// ABCFG 0xC0[15:12] = 0xF
// Enable "Power Saving Feature for A-Link Express Lanes"
// Enable "Power Saving Feature for GPP Lanes"
// ABCFG 0x90[19] = 1
// ABCFG 0x90[6] = 1
// RCINDC_Reg 0x65 [27:0] = 0xFFFFFFF
// ABCFG 0xC0[7:4] = 0x0
rwAlink (SB_ABCFG_REGC0 | (UINT32) (ABCFG << 29), ~BIT8, (BIT4 + BIT5 + BIT6 + BIT7));
rwAlink (SB_ABCFG_REGC0 | (UINT32) (ABCFG << 29), 0xFFFFFFFF, (BIT12 + BIT13 + BIT14 + BIT15));
rwAlink (SB_AX_INDXC_REG40, ~(BIT9 + BIT4), (BIT0 + BIT3 + BIT12));
rwAlink (RC_INDXC_REG40, ~(BIT9 + BIT4), (BIT0 + BIT3 + BIT12));
rwAlink ((SB_ABCFG_REG90 | (UINT32) (ABCFG << 29)), 0xFFFFFFFF, (BIT6 + BIT19));
rwAlink (RC_INDXC_REG65, 0xFFFFFFFF, 0x0fffffff);
rwAlink ((SB_ABCFG_REGC0 | (UINT32) (ABCFG << 29)), ~(BIT4 + BIT5 + BIT6 + BIT7), 0);
}
sbGppDisableUnusedPadMap ( pConfig );
}
/**
* PreInitGppLink - Enable GPP link training.
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID
PreInitGppLink (
IN AMDSBCFG* pConfig
)
{
UINT8 portMask[5] = {0x01,
0x00,
0x03,
0x07,
0x0F
};
UINT8 cfgMode;
UINT8 portId;
UINT32 reg32Value;
UINT16 tmp16Value;
// PCIE_GPP_ENABLE (abcfg:0xC0):
//
// GPP_LINK_CONFIG ([3:0]) PortA PortB PortC PortD Description
// ----------------------------------------------------------------------------------
// 0000 0-3 x4 Config
// 0001 N/A
// 0010 0-1 2-3 0 2:2 Config
// 0011 0-1 2 3 2:1:1 Config
// 0100 0 1 2 3 1:1:1:1 Config
//
// For A12 and above:
// ABCFG:0xC0[12] - Port A hold training (default 1)
// ABCFG:0xC0[13] - Port B hold training (default 1)
// ABCFG:0xC0[14] - Port C hold training (default 1)
// ABCFG:0xC0[15] - Port D hold training (default 1)
//
//
//
// Set port enable bit fields based on current GPP link configuration mode
//
cfgMode = (UINT8) pConfig->GppLinkConfig;
if ( cfgMode > GPP_CFGMODE_X1111 || cfgMode == 1 ) {
cfgMode = GPP_CFGMODE_X4000;
pConfig->GppLinkConfig = GPP_CFGMODE_X4000;
}
reg32Value = (UINT32) portMask[cfgMode];
// Mask out non-applicable ports according to the target link configuration mode
for ( portId = 0; portId < MAX_GPP_PORTS; portId++ ) {
pConfig->PORTCONFIG[portId].PortCfg.PortPresent &= (reg32Value >> portId) & BIT0;
}
//
// Deassert GPP reset and pull EP out of reset - Clear GPP_RESET (abcfg:0xC0[8] = 0)
//
tmp16Value = (UINT16) (~reg32Value << 12);
reg32Value = (UINT32) (tmp16Value + (reg32Value << 4) + cfgMode);
writeAlink (SB_ABCFG_REGC0 | (UINT32) (ABCFG << 29), reg32Value);
reg32Value = readAlink (0xC0 | (UINT32) (RCINDXC << 29));
writeAlink (0xC0 | (UINT32) (RCINDXC << 29), reg32Value | 0x400); // Set STRAP_F0_MSI_EN
// A-Link L1 Entry Delay Shortening
// AXINDP_Reg 0xA0[7:4] = 0x3
rwAlink (SB_AX_INDXP_REGA0, 0xFFFFFF0F, 0x30);
rwAlink (SB_AX_INDXP_REGB1, 0xFFFFFFFF, BIT19);
rwAlink (SB_AX_INDXP_REGB1, 0xFFFFFFFF, BIT28);
// RPR5.22 GPP L1 Entry Delay Shortening
// RCINDP_Reg 0xA0[7:4] = 0x1 Enter L1 sooner after ACK'ing PM request.
// This is done to reduce number of NAK received with L1 enabled.
for ( portId = 0; portId < MAX_GPP_PORTS; portId++ ) {
rwAlink (SB_RCINDXP_REGA0 | portId << 24, 0xFFFFFF0F, 0x10);
}
}
/**
* CheckGppLinkStatus - loop polling the link status for each GPP port
*
*
* Return: ToggleStatus[3:0] = Port bitmap for those need to clear De-emphasis
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
UINT8
CheckGppLinkStatus (
IN AMDSBCFG* pConfig
)
{
UINT32 retryCounter;
UINT32 portId;
UINT32 abIndex;
UINT32 Data32;
UINT8 portScanMap;
UINT8 portScanMap2;
UINT8 ToggleStatus;
UINT16 i;
SBGPPPORTCONFIG *portCfg;
portScanMap = 0;
retryCounter = MAX_TRAINING_RETRY;
ToggleStatus = 0;
// Obtain a list of ports to be checked
for ( portId = 0; portId < MAX_GPP_PORTS; portId++ ) {
portCfg = &pConfig->PORTCONFIG[portId].PortCfg;
if ( portCfg->PortPresent == TRUE && portCfg->PortDetected == FALSE ) {
portScanMap |= 1 << portId;
}
}
portScanMap2 = portScanMap;
//
// After training is enabled, Check LCSTATE for each port, if LCSTATE<= 4, then keep
// polling for up to 40ms. If LCSTATE still <= 4, then assume the port to be empty.
//
i = 400;
while ( --i && portScanMap2) {
for (portId = 0; portId < MAX_GPP_PORTS; portId++) {
portCfg = &pConfig->PORTCONFIG[portId].PortCfg;
if (((portCfg->PortHotPlug == FALSE) || ((portCfg->PortHotPlug == TRUE) && (pConfig->S3Resume == FALSE)) ) && (portScanMap2 & (1 << portId))) {
//
// Get port link state (reading LC_CURRENT_STATE of PCIEIND_P)
//
abIndex = SB_RCINDXP_REGA5 | (UINT32) (RCINDXP << 29) | (portId << 24);
Data32 = readAlink (abIndex) & 0x3F;
if ((UINT8) (Data32) > 4) {
portScanMap2 &= ~(1 << portId); // This port is not empty
break;
}
SbStall (100); // Delay 100us
}
}
}
portScanMap &= ~portScanMap2; // Mark remaining ports as empty
while ( --retryCounter && portScanMap ) {
for ( portId = 0; portId < MAX_GPP_PORTS; portId++ ) {
portCfg = &pConfig->PORTCONFIG[portId].PortCfg;
if (( portCfg->PortHotPlug == TRUE ) && ( pConfig->S3Resume )) {
continue;
}
if ( portCfg->PortPresent == TRUE && portCfg->PortDetected == FALSE ) {
//
// Get port link state (reading LC_CURRENT_STATE of PCIEIND_P)
//
SbStall (1000); // Delay 400us
abIndex = SB_RCINDXP_REGA5 | (UINT32) (RCINDXP << 29) | (portId << 24);
Data32 = readAlink (abIndex) & 0x3F3F3F3F;
if ( (UINT8) (Data32) == 0x10 ) {
portCfg->PortDetected = TRUE;
portScanMap &= ~(1 << portId);
} else {
for (i = 0; i < 4; i++) {
//
// Compliance mode (0x7), downgrade from Gen2 to Gen1 (*A12)
//
if ((UINT8) (Data32) == 0x29 || (UINT8) (Data32) == 0x2A || (UINT8) (Data32) == 0x7 ) {
ToggleStatus |= (1 << portId); // A11 only: need to toggle GPP reset
portScanMap &= ~(1 << portId);
}
Data32 >>= 8;
}
}
}
}
}
return ToggleStatus;
}
/**
* AfterGppLinkInit
* - Search for display device behind each GPP port
* - If the port is empty AND not hotplug-capable:
* * Turn off link training
* * (optional) Power down the port
* * Hide the configuration space (Turn off the port)
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID
AfterGppLinkInit (
IN AMDSBCFG* pConfig
)
{
UINT32 portId;
SBGPPPORTCONFIG *portCfg;
UINT32 regBusNumber;
UINT32 abValue;
UINT32 abIndex;
UINT32 i;
UINT32 Data32;
UINT8 bValue;
UINT8 cimGppGen2;
cimGppGen2 = pConfig->GppGen2;
#if SB_CIMx_PARAMETER == 0
cimGppGen2 = cimGppGen2Default;
#endif
bValue = GPP_EFUSE_LOCATION;
getEfuseStatus (&bValue);
if ( (bValue & GPP_GEN2_EFUSE_BIT) != 0 ) {
cimGppGen2 = FALSE;
} else {
pConfig->CoreGen2Enable = TRUE; // Output for platform use
}
//GPP Gen2 Speed Change
// if ((GPP Gen2 == enabled) and (RCINDP_Reg 0xA4[0] == 0x1)) {
// PCIe_Cfg 0x88[3:0] = 0x2
// RCINDP_Reg 0xA2[13] = 0x0
// RCINDP_Reg 0xC0[15] = 0x0
// RCINDP_Reg 0xA4[29] = 0x1
// } else {
// PCIe_Cfg 0x88[3:0] = 0x1
// RCINDP_Reg 0xA4[0] = 0x0
// RCINDP_Reg 0xA2[13] = 0x1
// RCINDP_Reg 0xC0[15] = 0x0
// RCINDP_Reg 0xA4[29] = 0x1
// }
for ( portId = 0; portId < MAX_GPP_PORTS; portId++ ) {
portCfg = &pConfig->PORTCONFIG[portId].PortCfg;
abValue = readAlink (SB_RCINDXP_REGA4 | portId << 24) & BIT0;
if (( cimGppGen2 == TRUE ) && (abValue == BIT0) && (portCfg->PortDetected == TRUE)) {
portCfg->PortIsGen2 = TRUE; // Output for platform use
sbGppForceGen2 (portId);
//_asm {jmp $};
SbStall (400); // Delay 400us
i = 500;
Data32 = 0;
while ( --i ) {
abIndex = SB_RCINDXP_REGA5 | (UINT32) (RCINDXP << 29) | (portId << 24);
Data32 = readAlink (abIndex) & 0x3F;
if ((UINT8) (Data32) == 0x10) {
break;
}
SbStall (400); // Delay 100us
}
if (!( (UINT8) (Data32) == 0x10 )) {
if (pConfig->GppCompliance == FALSE) {
portCfg->PortIsGen2 = FALSE; // Revert to default; output for platform use
sbGppForceGen1 (portId);
}
}
} else {
if (pConfig->GppCompliance == FALSE) {
sbGppForceGen1 (portId);
}
}
//RPR 5.9 Link Bandwidth Notification Capability Enable
//RCINDC 0xC1[0] = 1
//PCIe Cfg 0x68[10] = 0
//PCIe Cfg 0x68[11] = 0
rwAlink (SB_RCINDXC_REGC1, 0xFFFFFFFF, BIT0);
RWPCI (PCI_ADDRESS (0, GPP_DEV_NUM, portId, 0x68), AccWidthUint16, ~(BIT10 + BIT11), 0);
}
// Status = AGESA_SUCCESS;
pConfig->GppFoundGfxDev = 0;
abValue = readAlink (SB_ABCFG_REGC0 | (UINT32) (ABCFG << 29));
for ( portId = 0; portId < MAX_GPP_PORTS; portId++ ) {
portCfg = &pConfig->PORTCONFIG[portId].PortCfg;
// Check if there is GFX device behind each GPP port
if ( portCfg->PortDetected == TRUE ) {
regBusNumber = (SBTEMP_BUS << 16) + (SBTEMP_BUS << 8);
WritePCI (PCI_ADDRESS (0, GPP_DEV_NUM, portId, 0x18), AccWidthUint32, &regBusNumber);
// *** Stall ();
ReadPCI (PCI_ADDRESS (SBTEMP_BUS, 0, 0, 0x0B), AccWidthUint8, &bValue);
if ( bValue == 3 ) {
pConfig->GppFoundGfxDev |= (1 << portId);
}
regBusNumber = 0;
WritePCI (PCI_ADDRESS (0, GPP_DEV_NUM, portId, 0x18), AccWidthUint32, &regBusNumber);
}
// Mask off non-applicable ports
else if ( portCfg->PortPresent == FALSE ) {
abValue &= ~(1 << (portId + 4));
}
// Mask off empty port if the port is not hotplug-capable
else if ( portCfg->PortHotPlug == FALSE ) {
abValue &= ~(1 << (portId + 4));
}
// Clear STRAP_BIF_DE_EMPHASIS_SEL_x_GPP bit (abcfg:0x34[0, 4, 8, C][21]=0) to make hotplug working
if ( portCfg->PortHotPlug == TRUE ) {
rwAlink ((SB_ABCFG_REG340 + portId * 4) | (UINT32) (ABCFG << 29), ~BIT21, 0);
// RPR5.12 Hot Plug: PCIe Native Support
// RCINDP_Reg 0x10[3] = 0x1
// PCIe_Cfg 0x5A[8] = 0x1
// PCIe_Cfg 0x6C[6] = 0x1
// RCINDP_Reg 0x20[19] = 0x0
rwAlink ((SB_RCINDXP_REG10 | (UINT32) (RCINDXP << 29) | (portId << 24)), 0xFFFFFFFF, BIT3);
RWPCI (PCI_ADDRESS (0, GPP_DEV_NUM, portId, 0x5b), AccWidthUint8, 0xff, BIT0);
RWPCI (PCI_ADDRESS (0, GPP_DEV_NUM, portId, 0x6c), AccWidthUint8, 0xff, BIT6);
rwAlink ((SB_RCINDXP_REG20 | (UINT32) (RCINDXP << 29) | (portId << 24)), ~BIT19, 0);
}
}
if ( pConfig->GppUnhidePorts == FALSE ) {
if ((abValue & 0xF0) == 0) {
abValue = BIT8; // if all ports are empty set GPP_RESET
} else if ((abValue & 0xE0) != 0 && (abValue & 0x10) == 0) {
abValue |= BIT4; // PortA should always be visible whenever other ports are exist
}
// Update GPP_Portx_Enable (abcfg:0xC0[7:5])
writeAlink (SB_ABCFG_REGC0 | (UINT32) (ABCFG << 29), abValue);
}
//
// Common initialization for open GPP ports
//
for ( portId = 0; portId < MAX_GPP_PORTS; portId++ ) {
ReadPCI (PCI_ADDRESS (0, GPP_DEV_NUM, portId, 0x80), AccWidthUint8, &bValue);
if (bValue != 0xff) {
// Set pciCfg:PCIE_DEVICE_CNTL2[3:0] = 4'h6 (0x80[3:0])
bValue &= 0xf0;
bValue |= 0x06;
WritePCI (PCI_ADDRESS (0, GPP_DEV_NUM, portId, 0x80), AccWidthUint8, &bValue);
// Set PCIEIND_P:PCIE_RX_CNTL[RX_RCB_CPL_TIMEOUT_MODE] (0x70:[19]) = 1
abIndex = SB_RCINDXP_REG70 | (UINT32) (RCINDXP << 29) | (portId << 24);
abValue = readAlink (abIndex) | BIT19;
writeAlink (abIndex, abValue);
// Set PCIEIND_P:PCIE_TX_CNTL[TX_FLUSH_TLP_DIS] (0x20:[19]) = 0
abIndex = SB_RCINDXP_REG20 | (UINT32) (RCINDXP << 29) | (portId << 24);
abValue = readAlink (abIndex) & ~BIT19;
writeAlink (abIndex, abValue);
}
}
}
/**
* sbPcieGppLateInit - Late PCIE initialization for SB800 GPP component
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID
sbPcieGppLateInit (
IN AMDSBCFG* pConfig
)
{
UINT32 reg32Value;
UINT8 portId;
UINT8 busNum;
UINT8 aspmValue;
UINT8 reg8Value;
UINT8 cimGppPhyPllPowerDown;
reg8Value = 0x01;
//
// Configure ASPM
//
// writeAlink (0xC0 | (UINT32) (RCINDXC << 29), 0x400); // Set STRAP_F0_MSI_EN
aspmValue = (UINT8)pConfig->GppPortAspm;
cimGppPhyPllPowerDown = (UINT8) pConfig->GppPhyPllPowerDown;
#if SB_CIMx_PARAMETER == 0
aspmValue = cimGppPortAspmDefault;
cimGppPhyPllPowerDown = cimGppPhyPllPowerDownDefault;
#endif
for ( portId = 0; portId < MAX_GPP_PORTS; portId++ ) {
// write pci_reg3d with 0x01 to fix yellow mark for GPP bridge under Vista
// when native PCIE is enabled but MSI is not available
// SB02029: SB800 BIF/GPP allowing strap STRAP_BIF_INTERRUPT_PIN_SB controlled by AB reg
WritePCI (PCI_ADDRESS (0, 21, portId, 0x3d), AccWidthUint8, &reg8Value);
ReadPCI (PCI_ADDRESS (0, 21, portId, 0x19), AccWidthUint8, &busNum);
if (busNum != 0xFF) {
ReadPCI (PCI_ADDRESS (busNum, 0, 0, 0x00), AccWidthUint32, &reg32Value);
if (reg32Value != 0xffffffff) {
// Set ASPM on EP side
sbGppSetAspm (PCI_ADDRESS (busNum, 0, 0, 0), aspmValue & 0x3);
// Set ASPM on port side
sbGppSetAspm (PCI_ADDRESS (0, 21, portId, 0), aspmValue & 0x3);
}
}
aspmValue = aspmValue >> 2;
}
//
// Configure Lock HWInit registers
//
reg32Value = readAlink (SB_ABCFG_REGC0 | (UINT32) (ABCFG << 29));
if (reg32Value & 0xF0) {
reg32Value = readAlink (SB_RCINDXC_REG10 | (UINT32) (RCINDXC << 29));
writeAlink (SB_RCINDXC_REG10 | (UINT32) (RCINDXC << 29), reg32Value | BIT0); // Set HWINIT_WR_LOCK
if ( cimGppPhyPllPowerDown == TRUE ) {
//
// RPR 5.4 Power Saving Feature for GPP Lanes
//
UINT32 abValue;
// Set PCIE_P_CNTL in Alink PCIEIND space
abValue = readAlink (RC_INDXC_REG40 | (UINT32) (RCINDXC << 29));
abValue |= BIT12 + BIT3 + BIT0;
abValue &= ~(BIT9 + BIT4);
writeAlink (RC_INDXC_REG40 | (UINT32) (RCINDXC << 29), abValue);
}
}
//
// Configure Lock HWInit registers
//
reg32Value = readAlink (SB_ABCFG_REGC0 | (UINT32) (ABCFG << 29));
//
// Disable hidden register decode and serial number capability
//
reg32Value = readAlink (SB_ABCFG_REG330 | (UINT32) (ABCFG << 29));
writeAlink (SB_ABCFG_REG330 | (UINT32) (ABCFG << 29), reg32Value & ~(BIT26 + BIT10));
}
/**
* sbGppSetAspm - Set SPP ASPM
*
*
* @param[in] pciAddress PCI Address.
* @param[in] LxState Lane State.
*
*/
VOID
sbGppSetAspm (
IN UINT32 pciAddress,
IN UINT8 LxState
)
{
UINT8 pcieCapOffset;
UINT8 value8;
UINT8 maxFuncs;
UINT32 devBDF;
maxFuncs = 1;
ReadPCI (pciAddress + 0x0E, AccWidthUint8, &value8);
if (value8 & BIT7) {
maxFuncs = 8; // multi-function device
}
while (maxFuncs != 0) {
devBDF = pciAddress + (UINT32) ((maxFuncs - 1) << 16);
pcieCapOffset = sbFindPciCap (devBDF, PCIE_CAP_ID);
if (pcieCapOffset) {
// Read link capabilities register (0x0C[11:10] - ASPM support)
ReadPCI (devBDF + pcieCapOffset + 0x0D, AccWidthUint8, &value8);
if (value8 & BIT2) {
value8 = (value8 >> 2) & (BIT1 + BIT0);
// Set ASPM state in link control register
RWPCI (devBDF + pcieCapOffset + 0x10, AccWidthUint8, 0xffffffff, LxState & value8);
}
}
maxFuncs--;
}
}
/**
* sbFindPciCap - Find PCI Cap
*
*
* @param[in] pciAddress PCI Address.
* @param[in] targetCapId Target Cap ID.
*
*/
UINT8
sbFindPciCap (
IN UINT32 pciAddress,
IN UINT8 targetCapId
)
{
UINT8 NextCapPtr;
UINT8 CapId;
NextCapPtr = 0x34;
while (NextCapPtr != 0) {
ReadPCI (pciAddress + NextCapPtr, AccWidthUint8, &NextCapPtr);
if (NextCapPtr == 0xff) {
return 0;
}
if (NextCapPtr != 0) {
ReadPCI (pciAddress + NextCapPtr, AccWidthUint8, &CapId);
if (CapId == targetCapId) {
break;
} else {
NextCapPtr++;
}
}
}
return NextCapPtr;
}
/**
* sbGppForceGen2 - Set SPP to GENII
*
*
* @param[in] portId
*
*/
VOID
sbGppForceGen2 (
IN UINT32 portId
)
{
RWPCI (PCI_ADDRESS (0, GPP_DEV_NUM, portId, 0x88), AccWidthUint8, 0xf0, 0x02);
rwAlink (SB_RCINDXP_REGA2 | portId << 24, ~BIT13, 0);
rwAlink (SB_RCINDXP_REGC0 | portId << 24, ~BIT15, 0);
rwAlink (SB_RCINDXP_REGA4 | portId << 24, 0xFFFFFFFF, BIT29);
}
/**
* sbGppForceGen1 - Set SPP to GENI
*
*
* @param[in] portId
*
*/
VOID
sbGppForceGen1 (
IN UINT32 portId
)
{
RWPCI (PCI_ADDRESS (0, GPP_DEV_NUM, portId, 0x88), AccWidthUint8, 0xf0, 0x01);
rwAlink (SB_RCINDXP_REGA4 | portId << 24, ~BIT0, 0);
rwAlink (SB_RCINDXP_REGA2 | portId << 24, 0xFFFFFFFF, BIT13);
rwAlink (SB_RCINDXP_REGC0 | portId << 24, ~BIT15, 0);
rwAlink (SB_RCINDXP_REGA4 | portId << 24, 0xFFFFFFFF, BIT29);
}
/**
* sbGppDisableUnusedPadMap - Return GPP Pad Map
*
*
* @param[in] pConfig
*
*/
VOID
sbGppDisableUnusedPadMap (
IN AMDSBCFG* pConfig
)
{
UINT32 Data32;
UINT32 HoldData32;
SBGPPPORTCONFIG *portCfg;
UINT8 cimGppLaneReversal;
UINT8 cimAlinkPhyPllPowerDown;
UINT8 cimGppPhyPllPowerDown;
cimAlinkPhyPllPowerDown = (UINT8) pConfig->AlinkPhyPllPowerDown;
cimGppLaneReversal = (UINT8) pConfig->GppLaneReversal;
cimGppPhyPllPowerDown = (UINT8) pConfig->GppPhyPllPowerDown;
#if SB_CIMx_PARAMETER == 0
cimGppLaneReversal = cimGppLaneReversalDefault;
cimAlinkPhyPllPowerDown = cimAlinkPhyPllPowerDownDefault;
cimGppPhyPllPowerDown = cimGppPhyPllPowerDownDefault;
#endif
Data32 = 0;
HoldData32 = 0;
switch ( pConfig->GppLinkConfig ) {
case GPP_CFGMODE_X4000:
portCfg = &pConfig->PORTCONFIG[0].PortCfg;
if ( portCfg->PortDetected == FALSE ) {
Data32 |= 0x0f0f;
HoldData32 |= 0x1000;
}
break;
case GPP_CFGMODE_X2200:
portCfg = &pConfig->PORTCONFIG[0].PortCfg;
if ( portCfg->PortDetected == FALSE ) {
Data32 |= ( cimGppLaneReversal )? 0x0c0c:0x0303;
HoldData32 |= 0x1000;
}
portCfg = &pConfig->PORTCONFIG[1].PortCfg;
if ( portCfg->PortDetected == FALSE ) {
Data32 |= ( cimGppLaneReversal )? 0x0303:0x0c0c;
HoldData32 |= 0x2000;
}
break;
case GPP_CFGMODE_X2110:
portCfg = &pConfig->PORTCONFIG[0].PortCfg;
if ( portCfg->PortDetected == FALSE ) {
Data32 |= ( cimGppLaneReversal )? 0x0c0c:0x0303;
HoldData32 |= 0x1000;
}
portCfg = &pConfig->PORTCONFIG[1].PortCfg;
if ( portCfg->PortDetected == FALSE ) {
Data32 |= ( cimGppLaneReversal )? 0x0202:0x0404;
HoldData32 |= 0x2000;
}
portCfg = &pConfig->PORTCONFIG[2].PortCfg;
if ( portCfg->PortDetected == FALSE ) {
Data32 |= ( cimGppLaneReversal )? 0x0101:0x0808;
HoldData32 |= 0x4000;
}
break;
case GPP_CFGMODE_X1111:
portCfg = &pConfig->PORTCONFIG[0].PortCfg;
if ( portCfg->PortDetected == FALSE ) {
Data32 |= ( cimGppLaneReversal )? 0x0808:0x0101;
HoldData32 |= 0x1000;
}
portCfg = &pConfig->PORTCONFIG[1].PortCfg;
if ( portCfg->PortDetected == FALSE ) {
Data32 |= ( cimGppLaneReversal )? 0x0404:0x0202;
HoldData32 |= 0x2000;
}
portCfg = &pConfig->PORTCONFIG[2].PortCfg;
if ( portCfg->PortDetected == FALSE ) {
Data32 |= ( cimGppLaneReversal )? 0x0202:0x0404;
HoldData32 |= 0x4000;
}
portCfg = &pConfig->PORTCONFIG[3].PortCfg;
if ( portCfg->PortDetected == FALSE ) {
Data32 |= ( cimGppLaneReversal )? 0x0101:0x0808;
HoldData32 |= 0x8000;
}
break;
default:
break;
}
// RPR 5.11 Power Saving With GPP Disable
// ABCFG 0xC0[8] = 0x0
// ABCFG 0xC0[15:12] = 0xF
// Enable "Power Saving Feature for A-Link Express Lanes"
// Enable "Power Saving Feature for GPP Lanes"
// ABCFG 0x90[19] = 1
// ABCFG 0x90[6] = 1
// RCINDC_Reg 0x65 [27:0] = 0xFFFFFFF
// ABCFG 0xC0[7:4] = 0x0
if ( (Data32 & 0xf) == 0xf ) Data32 |= 0x0cff0000;
if ( cimAlinkPhyPllPowerDown && cimGppPhyPllPowerDown ) {
rwAlink (SB_ABCFG_REGC0 | (UINT32) (ABCFG << 29), ~BIT8, 0);
rwAlink (SB_ABCFG_REGC0 | (UINT32) (ABCFG << 29), 0xFFFFFFFF, HoldData32);
rwAlink (SB_AX_INDXC_REG40, ~(BIT9 + BIT4), (BIT0 + BIT3 + BIT12));
rwAlink (RC_INDXC_REG40, ~(BIT9 + BIT4), (BIT0 + BIT3 + BIT12));
rwAlink ((SB_ABCFG_REG90 | (UINT32) (ABCFG << 29)), 0xFFFFFFFF, (BIT6 + BIT19));
rwAlink (RC_INDXC_REG65, 0xFFFFFFFF, Data32);
}
}

81
src/vendorcode/amd/cimx/sb800/IOLIB.c Normal file
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@ -0,0 +1,81 @@
/*
*****************************************************************************
*
* This file is part of the coreboot project.
*
* Copyright (C) 2010 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
* ***************************************************************************
*
*/
#include "SBPLATFORM.h"
VOID
ReadIO (
IN UINT16 Address,
IN UINT8 OpFlag,
IN VOID* Value
)
{
OpFlag = OpFlag & 0x7f;
switch ( OpFlag ) {
case AccWidthUint8:
*(UINT8*)Value = ReadIo8 (Address);
break;
case AccWidthUint16:
*(UINT16*)Value = ReadIo16 (Address);
break;
case AccWidthUint32:
*(UINT32*)Value = ReadIo32 (Address);
break;
}
}
VOID
WriteIO (
IN UINT16 Address,
IN UINT8 OpFlag,
IN VOID* Value
)
{
OpFlag = OpFlag & 0x7f;
switch ( OpFlag ) {
case AccWidthUint8:
WriteIo8 (Address, *(UINT8*)Value);
break;
case AccWidthUint16:
WriteIo16 (Address, *(UINT16*)Value);
break;
case AccWidthUint32:
WriteIo32 (Address, *(UINT32*)Value);
break;
}
}
VOID
RWIO (
IN UINT16 Address,
IN UINT8 OpFlag,
IN UINT32 Mask,
IN UINT32 Data
)
{
UINT32 Result;
ReadIO (Address, OpFlag, &Result);
Result = (Result & Mask) | Data;
WriteIO (Address, OpFlag, &Result);
}

37
src/vendorcode/amd/cimx/sb800/LEGACY.c Normal file
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/*
*****************************************************************************
*
* This file is part of the coreboot project.
*
* Copyright (C) 2010 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
* ***************************************************************************
*
*/
#include "SBPLATFORM.h"
UINT32
GetFixUp (
OUT VOID
)
{
AMD_CONFIG_PARAMS* Result;
Result = (AMD_CONFIG_PARAMS*) getConfigPointer ();
if ( Result->ImageBasePtr > 0x100000 && Result->ImageBasePtr < 0xFF000000 ) {
return 0;
}
return Result->ImageBasePtr;
}

86
src/vendorcode/amd/cimx/sb800/MEMLIB.c Normal file
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/*
*****************************************************************************
*
* This file is part of the coreboot project.
*
* Copyright (C) 2010 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
* ***************************************************************************
*
*/
#include "SBPLATFORM.h"
VOID
ReadMEM (
IN UINT32 Address,
IN UINT8 OpFlag,
IN VOID* Value
)
{
OpFlag = OpFlag & 0x7f;
switch ( OpFlag ) {
case AccWidthUint8:
*((UINT8*)Value) = *((UINT8*) ((UINTN)Address));
break;
case AccWidthUint16:
//*((UINT16*)Value) = *((UINT16*) ((UINTN)Address)); //gcc break strict-aliasing rules
*((UINT8*)Value) = *((UINT8*) ((UINTN)Address));
*((UINT8*)Value + 1) = *((UINT8*)((UINTN)Address) + 1);
break;
case AccWidthUint32:
*((UINT32*)Value) = *((UINT32*) ((UINTN)Address));
break;
}
}
VOID
WriteMEM (
IN UINT32 Address,
IN UINT8 OpFlag,
IN VOID* Value
)
{
OpFlag = OpFlag & 0x7f;
switch ( OpFlag ) {
case AccWidthUint8 :
*((UINT8*) ((UINTN)Address)) = *((UINT8*)Value);
break;
case AccWidthUint16:
//*((UINT16*) ((UINTN)Address)) = *((UINT16*)Value); //gcc break strict-aliasing rules
*((UINT8*)((UINTN)Address)) = *((UINT8*)Value);
*((UINT8*)((UINTN)Address) + 1) = *((UINT8*)Value + 1);
break;
case AccWidthUint32:
*((UINT32*) ((UINTN)Address)) = *((UINT32*)Value);
break;
}
}
VOID
RWMEM (
IN UINT32 Address,
IN UINT8 OpFlag,
IN UINT32 Mask,
IN UINT32 Data
)
{
UINT32 Result;
ReadMEM (Address, OpFlag, &Result);
Result = (Result & Mask) | Data;
WriteMEM (Address, OpFlag, &Result);
}

75
src/vendorcode/amd/cimx/sb800/Makefile.inc Normal file
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#
# This file is part of the coreboot project.
#
# Copyright (C) 2010 Advanced Micro Devices, Inc.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; version 2 of the License.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
#
# CIMX Root directory
CIMX_ROOT = src/vendorcode/amd/cimx
CIMX_INC = -I$(src)/mainboard/$(MAINBOARDDIR)
CIMX_INC += -I$(src)/southbridge/amd/cimx_wrapper/sb800
CIMX_INC += -I$(CIMX_ROOT)/sb800
#TODO merge withagesa lib functions
CIMX_INC += -I$(CIMX_ROOT)/lib
# CIMX LIB files
romstage-y += MEMLIB.c
romstage-y += PCILIB.c
romstage-y += IOLIB.c
romstage-y += PMIOLIB.c
romstage-y += AMDLIB.c
romstage-y += SBPELIB.c
romstage-y += AMDSBLIB.c
romstage-y += SBPOR.c
romstage-y += ECLIB.c
romstage-y += EC.c
ramstage-y += DISPATCHER.c
ramstage-y += ACPILIB.c
ramstage-y += AZALIA.c
ramstage-y += DISPATCHER.c
ramstage-y += ECfanc.c
ramstage-y += ECfanLIB.c
ramstage-y += GEC.c
ramstage-y += Gpp.c
ramstage-y += PMIO2LIB.c
ramstage-y += SATA.c
ramstage-y += SBCMN.c
ramstage-y += SBMAIN.c
ramstage-y += SBPOR.c
ramstage-y += MEMLIB.c
ramstage-y += PCILIB.c
ramstage-y += IOLIB.c
ramstage-y += PMIOLIB.c
ramstage-y += AMDLIB.c
ramstage-y += SBPELIB.c
ramstage-y += AMDSBLIB.c
ramstage-y += ECLIB.c
ramstage-y += EC.c
ramstage-y += SMM.c
ramstage-y += USB.c
#ramstage-y += LEGACY.c
#ramstage-y += SbModInf.c
CIMX_CFLAGS =
export CIMX_ROOT
export CIMX_INC
export CIMX_CFLAGS
CC := $(CC) $(CIMX_INC)
#######################################################################

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src/vendorcode/amd/cimx/sb800/OEM.h Normal file
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/*
*****************************************************************************
*
* This file is part of the coreboot project.
*
* Copyright (C) 2010 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
* ***************************************************************************
*
*/
#define BIOS_SIZE 0x04 //04 - 1MB
#define LEGACY_FREE 0x00
#define ACPI_SLEEP_TRAP 0x01
//#define SPREAD_SPECTRUM_EPROM_LOAD 0x01
/**
* Module Specific Defines for platform BIOS
*
*/
/**
* PCIEX_BASE_ADDRESS - Define PCIE base address
*
* @param[Option] MOVE_PCIEBAR_TO_F0000000 Set PCIe base address to 0xF7000000
*/
#ifdef MOVE_PCIEBAR_TO_F0000000
#define PCIEX_BASE_ADDRESS 0xF7000000
#else
#define PCIEX_BASE_ADDRESS 0xE0000000
#endif
/**
* SMBUS0_BASE_ADDRESS - Smbus base address
*
*/
#ifndef SMBUS0_BASE_ADDRESS
#define SMBUS0_BASE_ADDRESS 0xB00
#endif
/**
* SMBUS1_BASE_ADDRESS - Smbus1 (ASF) base address
*
*/
#ifndef SMBUS1_BASE_ADDRESS
#define SMBUS1_BASE_ADDRESS 0xB20
#endif
/**
* GEC_BASE_ADDRESS - Gec Shadow ROM base address
*
*/
#ifndef GEC_BASE_ADDRESS
#define GEC_BASE_ADDRESS 0xFED61000
#endif
/**
* SIO_PME_BASE_ADDRESS - Super IO PME base address
*
*/
#ifndef SIO_PME_BASE_ADDRESS
#define SIO_PME_BASE_ADDRESS 0xE00
#endif
/**
* SPI_BASE_ADDRESS - SPI controller (ROM) base address
*
*/
#ifndef SPI_BASE_ADDRESS
#define SPI_BASE_ADDRESS 0xFEC10000
#endif
/**
* WATCHDOG_TIMER_BASE_ADDRESS - WATCHDOG timer base address
*
*/
#ifndef WATCHDOG_TIMER_BASE_ADDRESS
#define WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0 // Watchdog Timer Base Address
#endif
/**
* HPET_BASE_ADDRESS - HPET base address
*
*/
#ifndef HPET_BASE_ADDRESS
#define HPET_BASE_ADDRESS 0xFED00000 // HPET Base address
#endif
/**
* ALT_ADDR_400 - For some BIOS codebases which use 0x400 as ACPI base address
*
*/
#ifdef ALT_ADDR_400
#define ACPI_BLK_BASE 0x400
#else
#define ACPI_BLK_BASE 0x800
#endif
#define PM1_STATUS_OFFSET 0x00
#define PM1_ENABLE_OFFSET 0x02
#define PM1_CONTROL_OFFSET 0x04
#define PM_TIMER_OFFSET 0x08
#define CPU_CONTROL_OFFSET 0x10
#define EVENT_STATUS_OFFSET 0x20
#define EVENT_ENABLE_OFFSET 0x24
/**
* PM1_EVT_BLK_ADDRESS - ACPI power management Event Block base address
*
*/
#define PM1_EVT_BLK_ADDRESS ACPI_BLK_BASE + PM1_STATUS_OFFSET // AcpiPm1EvtBlkAddr
/**
* PM1_CNT_BLK_ADDRESS - ACPI power management Control block base address
*
*/
#define PM1_CNT_BLK_ADDRESS ACPI_BLK_BASE + PM1_CONTROL_OFFSET // AcpiPm1CntBlkAddr
/**
* PM1_TMR_BLK_ADDRESS - ACPI power management Timer block base address
*
*/
#define PM1_TMR_BLK_ADDRESS ACPI_BLK_BASE + PM_TIMER_OFFSET // AcpiPmTmrBlkAddr
/**
* CPU_CNT_BLK_ADDRESS - ACPI power management CPU Control block base address
*
*/
#define CPU_CNT_BLK_ADDRESS ACPI_BLK_BASE + CPU_CONTROL_OFFSET // CpuControlBlkAddr
/**
* GPE0_BLK_ADDRESS - ACPI power management General Purpose Event block base address
*
*/
#define GPE0_BLK_ADDRESS ACPI_BLK_BASE + EVENT_STATUS_OFFSET // AcpiGpe0BlkAddr
/**
* SMI_CMD_PORT - ACPI SMI Command block base address
*
*/
#define SMI_CMD_PORT 0xB0 // SmiCmdPortAddr
/**
* ACPI_PMA_CNT_BLK_ADDRESS - ACPI power management additional control block base address
*
*/
#define ACPI_PMA_CNT_BLK_ADDRESS 0xFE00 // AcpiPmaCntBlkAddr
/**
* SATA_IDE_MODE_SSID - Sata controller IDE mode SSID.
* Define value for SSID while SATA controller set to IDE mode.
*/
#ifndef SATA_IDE_MODE_SSID
#define SATA_IDE_MODE_SSID 0x43901002
#endif
/**
* SATA_RAID_MODE_SSID - Sata controller RAID mode SSID.
* Define value for SSID while SATA controller set to RAID mode.
*/
#ifndef SATA_RAID_MODE_SSID
#define SATA_RAID_MODE_SSID 0x43921002
#endif
/**
* SATA_RAID5_MODE_SSID - Sata controller RAID5 mode SSID.
* Define value for SSID while SATA controller set to RAID5 mode.
*/
#ifndef SATA_RAID5_MODE_SSID
#define SATA_RAID5_MODE_SSID 0x43931002
#endif
/**
* SATA_AHCI_MODE_SSID - Sata controller AHCI mode SSID.
* Define value for SSID while SATA controller set to AHCI mode.
*/
#ifndef SATA_AHCI_SSID
#define SATA_AHCI_SSID 0x43911002
#endif
/**
* OHCI_SSID - All SB OHCI controllers SSID value.
*
*/
#ifndef OHCI_SSID
#define OHCI_SSID 0x43971002
#endif
/**
* EHCI_SSID - All SB EHCI controllers SSID value.
*
*/
#ifndef EHCI_SSID
#define EHCI_SSID 0x43961002
#endif
/**
* OHCI4_SSID - OHCI (USB 1.1 mode *HW force) controllers SSID value.
*
*/
#ifndef OHCI4_SSID
#define OHCI4_SSID 0x43991002
#endif
/**
* SMBUS_SSID - Smbus controller (South Bridge device 0x14 function 0) SSID value.
*
*/
#ifndef SMBUS_SSID
#define SMBUS_SSID 0x43851002
#endif
/**
* IDE_SSID - SATA IDE controller (South Bridge device 0x14 function 1) SSID value.
*
*/
#ifndef IDE_SSID
#define IDE_SSID 0x439C1002
#endif
/**
* AZALIA_SSID - AZALIA controller (South Bridge device 0x14 function 2) SSID value.
*
*/
#ifndef AZALIA_SSID
#define AZALIA_SSID 0x43831002
#endif
/**
* LPC_SSID - LPC controller (South Bridge device 0x14 function 3) SSID value.
*
*/
#ifndef LPC_SSID
#define LPC_SSID 0x439D1002
#endif
/**
* PCIB_SSID - PCIB controller (South Bridge device 0x14 function 4) SSID value.
*
*/
#ifndef PCIB_SSID
#define PCIB_SSID 0x43841002
#endif
/**
* USB_PLL_Voltage - CG2 Clock voltage setting.
*
*/
#ifndef USB_PLL_Voltage
#define USB_PLL_Voltage 0x10
#endif
/**
* Spread_Spectrum_Type
*
* - 0 : Normal platform
* - 1 : Ontario platform
*/
#ifndef Spread_Spectrum_Type
#define Spread_Spectrum_Type 0x00
#endif

76
src/vendorcode/amd/cimx/sb800/PCILIB.c Normal file
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/*
*****************************************************************************
*
* This file is part of the coreboot project.
*
* Copyright (C) 2010 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
* ***************************************************************************
*
*/
#include "SBPLATFORM.h"
VOID
ReadPCI (
IN UINT32 Address,
IN UINT8 OpFlag,
IN VOID* Value
)
{
OpFlag = OpFlag & 0x7f;
if ( (UINT16)Address < 0xff ) {
//Normal Config Access
UINT32 AddrCf8;
AddrCf8 = (1 << 31) + ((Address >> 8) & 0x0FFFF00) + (Address & 0xFC);
WriteIO (0xCf8, AccWidthUint32, &AddrCf8);
ReadIO ((UINT16) (0xCfC + (Address & 0x3)), OpFlag, Value);
}
}
VOID
WritePCI (
IN UINT32 Address,
IN UINT8 OpFlag,
IN VOID* Value
)
{
OpFlag = OpFlag & 0x7f;
if ( (UINT16)Address < 0xff ) {
//Normal Config Access
UINT32 AddrCf8;
AddrCf8 = (1 << 31) + ((Address >> 8)&0x0FFFF00) + (Address & 0xFC);
WriteIO (0xCf8, AccWidthUint32, &AddrCf8);
WriteIO ((UINT16) (0xCfC + (Address & 0x3)), OpFlag, Value);
}
}
VOID
RWPCI (
IN UINT32 Address,
IN UINT8 OpFlag,
IN UINT32 Mask,
IN UINT32 Data
)
{
UINT32 Result;
Result = 0;
OpFlag = OpFlag & 0x7f;
ReadPCI (Address, OpFlag, &Result);
Result = (Result & Mask) | Data;
WritePCI (Address, OpFlag, &Result);
}

120
src/vendorcode/amd/cimx/sb800/PMIO2LIB.c Normal file
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/**
* @file
*
* Southbridge PMIO2 access common routine
*
*/
/*
*****************************************************************************
*
* This file is part of the coreboot project.
*
* Copyright (C) 2010 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
* ***************************************************************************
*
*/
#include "SBPLATFORM.h"
/*----------------------------------------------------------------------------------------*/
/**
* Read PMIO2
*
*
*
* @param[in] Address - PMIO2 Offset value
* @param[in] OpFlag - Access sizes
* @param[in] Value - Read Data Buffer
*
*/
VOID
ReadPMIO2 (
IN UINT8 Address,
IN UINT8 OpFlag,
IN VOID* Value
)
{
UINT8 i;
OpFlag = OpFlag & 0x7f;
if ( OpFlag == 0x02 ) {
OpFlag = 0x03;
}
for ( i = 0; i <= OpFlag; i++ ) {
WriteIO (0xCD0, AccWidthUint8, &Address); // SB_IOMAP_REGCD0
Address++;
ReadIO (0xCD1, AccWidthUint8, (UINT8 *) Value + i); // SB_IOMAP_REGCD1
}
}
/*----------------------------------------------------------------------------------------*/
/**
* Write PMIO 2
*
*
*
* @param[in] Address - PMIO2 Offset value
* @param[in] OpFlag - Access sizes
* @param[in] Value - Write Data Buffer
*
*/
VOID
WritePMIO2 (
IN UINT8 Address,
IN UINT8 OpFlag,
IN VOID* Value
)
{
UINT8 i;
OpFlag = OpFlag & 0x7f;
if ( OpFlag == 0x02 ) {
OpFlag = 0x03;
}
for ( i = 0; i <= OpFlag; i++ ) {
WriteIO (0xCD0, AccWidthUint8, &Address); // SB_IOMAP_REGCD0
Address++;
WriteIO (0xCD1, AccWidthUint8, (UINT8 *)Value + i); // SB_IOMAP_REGCD1
}
}
/*----------------------------------------------------------------------------------------*/
/**
* RWPMIO2 - Read/Write PMIO2
*
*
*
* @param[in] Address - PMIO2 Offset value
* @param[in] OpFlag - Access sizes
* @param[in] AndMask - Data And Mask 32 bits
* @param[in] OrMask - Data OR Mask 32 bits
*
*/
VOID
RWPMIO2 (
IN UINT8 Address,
IN UINT8 OpFlag,
IN UINT32 AndMask,
IN UINT32 OrMask
)
{
UINT32 Result;
OpFlag = OpFlag & 0x7f;
ReadPMIO2 (Address, OpFlag, &Result);
Result = (Result & AndMask) | OrMask;
WritePMIO2 (Address, OpFlag, &Result);
}

119
src/vendorcode/amd/cimx/sb800/PMIOLIB.c Normal file
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/**
* @file
*
* Southbridge PMIO access common routine
*
*/
/*
*****************************************************************************
*
* This file is part of the coreboot project.
*
* Copyright (C) 2010 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
* ***************************************************************************
*
*/
#include "SBPLATFORM.h"
/*----------------------------------------------------------------------------------------*/
/**
* Read PMIO
*
*
*
* @param[in] Address - PMIO Offset value
* @param[in] OpFlag - Access sizes
* @param[in] Value - Read Data Buffer
*
*/
VOID
ReadPMIO (
IN UINT8 Address,
IN UINT8 OpFlag,
IN VOID* Value
)
{
UINT8 i;
OpFlag = OpFlag & 0x7f;
if ( OpFlag == 0x02 ) {
OpFlag = 0x03;
}
for ( i = 0; i <= OpFlag; i++ ) {
WriteIO (0xCD6, AccWidthUint8, &Address); // SB_IOMAP_REGCD6
Address++;
ReadIO (0xCD7, AccWidthUint8, (UINT8 *)Value + i); // SB_IOMAP_REGCD7
}
}
/*----------------------------------------------------------------------------------------*/
/**
* Write PMIO
*
*
*
* @param[in] Address - PMIO Offset value
* @param[in] OpFlag - Access sizes
* @param[in] Value - Write Data Buffer
*
*/
VOID
WritePMIO (
IN UINT8 Address,
IN UINT8 OpFlag,
IN VOID* Value
)
{
UINT8 i;
OpFlag = OpFlag & 0x7f;
if ( OpFlag == 0x02 ) {
OpFlag = 0x03;
}
for ( i = 0; i <= OpFlag; i++ ) {
WriteIO (0xCD6, AccWidthUint8, &Address); // SB_IOMAP_REGCD6
Address++;
WriteIO (0xCD7, AccWidthUint8, (UINT8 *)Value + i); // SB_IOMAP_REGCD7
}
}
/*----------------------------------------------------------------------------------------*/
/**
* RWPMIO - Read/Write PMIO
*
*
*
* @param[in] Address - PMIO Offset value
* @param[in] OpFlag - Access sizes
* @param[in] AndMask - Data And Mask 32 bits
* @param[in] OrMask - Data OR Mask 32 bits
*
*/
VOID
RWPMIO (
IN UINT8 Address,
IN UINT8 OpFlag,
IN UINT32 AndMask,
IN UINT32 OrMask
)
{
UINT32 Result;
OpFlag = OpFlag & 0x7f;
ReadPMIO (Address, OpFlag, &Result);
Result = (Result & AndMask) | OrMask;
WritePMIO (Address, OpFlag, &Result);
}

665
src/vendorcode/amd/cimx/sb800/SATA.c Normal file
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/**
* @file
*
* Config Southbridge SATA controller
*
* Init SATA features.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: CIMx-SB
* @e sub-project:
* @e \$Revision:$ @e \$Date:$
*
*/
/*
*****************************************************************************
*
* This file is part of the coreboot project.
*
* Copyright (C) 2010 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
* ***************************************************************************
*
*/
#include "SBPLATFORM.h"
//
// Declaration of local functions
//
VOID sataSetIrqIntResource (IN AMDSBCFG* pConfig);
VOID sataBar5setting (IN AMDSBCFG* pConfig, IN UINT32 *pBar5);
VOID shutdownUnconnectedSataPortClock (IN AMDSBCFG* pConfig, IN UINT32 ddBar5);
VOID sataDriveDetection (IN AMDSBCFG* pConfig, IN UINT32 *pBar5);
/**
* sataSetIrqIntResource - Config SATA IRQ/INT# resource
*
*
* - Private function
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID
sataSetIrqIntResource (
IN AMDSBCFG* pConfig
)
{
UINT8 dbValue;
// IRQ14/IRQ15 come from IDE or SATA
dbValue = 0x08;
WriteIO (SB_IOMAP_REGC00, AccWidthUint8, &dbValue);
ReadIO (SB_IOMAP_REGC01, AccWidthUint8, &dbValue);
dbValue = dbValue & 0x0F;
if (pConfig->SataClass == 3) {
dbValue = dbValue | 0x50;
} else {
if (pConfig->SataIdeMode == 1) {
// Both IDE & SATA set to Native mode
dbValue = dbValue | 0xF0;
}
}
WriteIO (SB_IOMAP_REGC01, AccWidthUint8, &dbValue);
}
/**
* sataBar5setting - Config SATA BAR5
*
* - Private function
*
* @param[in] pConfig - Southbridge configuration structure pointer.
* @param[in] *pBar5 - SATA BAR5 buffer.
*
*/
VOID
sataBar5setting (
IN AMDSBCFG* pConfig,
IN UINT32 *pBar5
)
{
//Get BAR5 value
ReadPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG24), AccWidthUint32, pBar5);
//Assign temporary BAR if is not already assigned
if ( (*pBar5 == 0) || (*pBar5 == - 1) ) {
//assign temporary BAR5
if ( (pConfig->TempMMIO == 0) || (pConfig->TempMMIO == - 1) ) {
*pBar5 = 0xFEC01000;
} else {
*pBar5 = pConfig->TempMMIO;
}
WritePCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG24), AccWidthUint32, pBar5);
}
//Clear Bits 9:0
*pBar5 = *pBar5 & 0xFFFFFC00;
}
/**
* shutdownUnconnectedSataPortClock - Shutdown unconnected Sata port clock
*
* - Private function
*
* @param[in] pConfig Southbridge configuration structure pointer.
* @param[in] ddBar5 Sata BAR5 base address.
*
*/
VOID
shutdownUnconnectedSataPortClock (
IN AMDSBCFG* pConfig,
IN UINT32 ddBar5
)
{
UINT8 dbPortNum;
UINT8 dbPortSataStatus;
UINT8 NumOfPorts;
UINT8 cimSataClkAutoOff;
cimSataClkAutoOff = (UINT8) pConfig->SataClkAutoOff;
#if SB_CIMx_PARAMETER == 0
cimSataClkAutoOff = cimSataClkAutoOffDefault;
#endif
NumOfPorts = 0;
if ( cimSataClkAutoOff == TRUE ) {
for ( dbPortNum = 0; dbPortNum < 6; dbPortNum++ ) {
ReadMEM (ddBar5 + SB_SATA_BAR5_REG128 + (dbPortNum * 0x80), AccWidthUint8, &dbPortSataStatus);
// Shutdown the clock for the port and do the necessary port reporting changes.
// ?? Error port status should be 1 not 3
if ( ((dbPortSataStatus & 0x0F) != 0x03) && (! ((pConfig->SataEspPort) & (1 << dbPortNum))) ) {
RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 2), AccWidthUint8, 0xFF, (1 << dbPortNum));
RWMEM (ddBar5 + SB_SATA_BAR5_REG0C, AccWidthUint8, ~(1 << dbPortNum), 00);
}
} //end of for (dbPortNum=0;dbPortNum<6;dbPortNum++)
ReadMEM (ddBar5 + SB_SATA_BAR5_REG0C, AccWidthUint8, &dbPortSataStatus);
//if all ports are in disabled state, report atleast one port
if ( (dbPortSataStatus & 0x3F) == 0) {
RWMEM (ddBar5 + SB_SATA_BAR5_REG0C, AccWidthUint8, (UINT32) ~(0x3F), 01);
}
ReadMEM (ddBar5 + SB_SATA_BAR5_REG0C, AccWidthUint8, &dbPortSataStatus);
for (dbPortNum = 0; dbPortNum < 6; dbPortNum ++) {
if (dbPortSataStatus & (1 << dbPortNum)) {
NumOfPorts++;
}
}
if ( NumOfPorts == 0) {
NumOfPorts = 0x01;
}
RWMEM (ddBar5 + SB_SATA_BAR5_REG00, AccWidthUint8, 0xE0, NumOfPorts - 1);
} //end of SataClkAuto Off option
}
/**
* Table for class code of SATA Controller in different modes
*
*
*
*
*/
UINT32 sataIfCodeTable[] =
{
0x01018F40, //sata class ID of IDE
0x01040040, //sata class ID of RAID
0x01060140, //sata class ID of AHCI
0x01018A40, //sata class ID of Legacy IDE
0x01018F40, //sata class ID of IDE to AHCI mode
};
/**
* Table for device id of SATA Controller in different modes
*
*
*
*
*/
UINT16 sataDeviceIDTable[] =
{
0x4390, //sata device ID of IDE
0x4392, //sata device ID of RAID
0x4391, //sata class ID of AHCI
0x4390, //sata device ID of Legacy IDE
0x4390, //sata device ID of IDE->AHCI mode
};
/**
* Table for Sata Phy Fine Setting
*
*
*
*
*/
SATAPHYSETTING sataPhyTable[] =
{
{0x3006, 0x0056A607},
{0x2006, 0x00061400},
{0x1006, 0x00061302},
{0x3206, 0x0056A607},
{0x2206, 0x00061400},
{0x1206, 0x00061302},
{0x3406, 0x0056A607},
{0x2406, 0x00061402},
{0x1406, 0x00064300},
{0x3606, 0x0056A607},
{0x2606, 0x00061402},
{0x1606, 0x00064300},
{0x3806, 0x0056A700},
{0x2806, 0x00061502},
{0x1806, 0x00064302},
{0x3A06, 0x0056A700},
{0x2A06, 0x00061502},
{0x1A06, 0x00064302}
};
/**
* sataInitBeforePciEnum - Config SATA controller before PCI emulation
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID
sataInitBeforePciEnum (
IN AMDSBCFG* pConfig
)
{
UINT32 ddTempVar;
UINT32 ddValue;
UINT32 *tempptr;
UINT16 *pDeviceIdptr;
UINT32 dwDeviceId;
UINT8 dbValue;
UINT8 pValue;
UINT16 i;
SATAPHYSETTING *pPhyTable;
ddTempVar = NULL;
// BIT0 Enable write access to PCI header (reg 08h-0Bh) by setting SATA PCI register 40h
// BIT4: Disable fast boot
RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, 0xff, BIT0 + BIT2 + BIT4);
// BIT0 Enable write access to PCI header (reg 08h-0Bh) by setting IDE PCI register 40h
RWPCI (((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG40), AccWidthUint8 | S3_SAVE, 0xff, BIT0);
RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 2), AccWidthUint8 | S3_SAVE, 0, pConfig->SataPortPower);
dbValue = (UINT8)pConfig->SataClass;
if (dbValue == AHCI_MODE_4394) {
dbValue = AHCI_MODE;
}
if (dbValue == IDE_TO_AHCI_MODE_4394) {
dbValue = IDE_TO_AHCI_MODE;
}
// Disable PATA MSI
RWPCI (((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG34), AccWidthUint8 | S3_SAVE, 0x00, 0x00);
RWPCI (((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG06), AccWidthUint8 | S3_SAVE, 0xEF, 0x00);
// Get the appropriate class code from the table and write it to PCI register 08h-0Bh
// Set the appropriate SATA class based on the input parameters
// SATA IDE Controller Class ID & SSID
tempptr = (UINT32 *) FIXUP_PTR (&sataIfCodeTable[0]);
if ( (pConfig->SataIdeMode == 1) && (pConfig->SataClass != 3) ) {
ddValue = tempptr[0];
// Write the class code to IDE PCI register 08h-0Bh
RWPCI (((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG08), AccWidthUint32 | S3_SAVE, 0, ddValue);
}
ddValue = tempptr[dbValue];
// Write the class code to SATA PCI register 08h-0Bh
RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG08), AccWidthUint32 | S3_SAVE, 0, ddValue);
if ( pConfig->SataClass == LEGACY_IDE_MODE ) {
//Set PATA controller to native mode
RWPCI (((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG09), AccWidthUint8 | S3_SAVE, 0x00, 0x08F);
}
if (pConfig->BuildParameters.IdeSsid != NULL ) {
RWPCI ((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.IdeSsid);
}
// SATA Controller Class ID & SSID
pDeviceIdptr = (UINT16 *) FIXUP_PTR (&sataDeviceIDTable[0]);
if ( pConfig->BuildParameters.SataIDESsid != NULL ) {
ddTempVar = pConfig->BuildParameters.SataIDESsid;
}
dwDeviceId = pDeviceIdptr[dbValue];
if ( pConfig->SataClass == RAID_MODE) {
if ( pConfig->BuildParameters.SataRAID5Ssid != NULL ) {
ddTempVar = pConfig->BuildParameters.SataRAID5Ssid;
}
dwDeviceId = V_SB_SATA_RAID5_DID;
pValue = SATA_EFUSE_LOCATION;
getEfuseStatus (&pValue);
if (( pValue & SATA_EFUSE_BIT ) || ( pConfig->SataForceRaid == 1 )) {
dwDeviceId = V_SB_SATA_RAID_DID;
if ( pConfig->BuildParameters.SataRAIDSsid != NULL ) {
ddTempVar = pConfig->BuildParameters.SataRAIDSsid;
}
}
}
if ( ((pConfig->SataClass) == AHCI_MODE) || ((pConfig->SataClass) == IDE_TO_AHCI_MODE) ||
((pConfig->SataClass) == AHCI_MODE_4394) || ((pConfig->SataClass) == IDE_TO_AHCI_MODE_4394) ) {
if ( pConfig->BuildParameters.SataAHCISsid != NULL ) {
ddTempVar = pConfig->BuildParameters.SataAHCISsid;
}
}
RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG02), AccWidthUint16 | S3_SAVE, 0, dwDeviceId);
if ( ddTempVar != NULL ) {
RWPCI ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG2C, AccWidthUint32 | S3_SAVE, 0x00, ddTempVar);
}
// SATA IRQ Resource
sataSetIrqIntResource (pConfig);
// 8.4 SATA PHY Programming Sequence
pPhyTable = (SATAPHYSETTING*)FIXUP_PTR (&sataPhyTable[0]);
for (i = 0; i < (sizeof (sataPhyTable) / sizeof (SATAPHYSETTING)); i++) {
RWPCI ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG84, AccWidthUint16 | S3_SAVE, ~(BIT1 + BIT2 + BIT9 + BIT10 + BIT11 + BIT12 + BIT13 + BIT14), pPhyTable->wPhyCoreControl);
RWPCI ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG94, AccWidthUint32 | S3_SAVE, 0x00, pPhyTable->dwPhyFineTune);
++pPhyTable;
}
// CallBackToOEM (SATA_PHY_PROGRAMMING, NULL, pConfig);
RWPCI (((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG40), AccWidthUint8 | S3_SAVE, ~BIT0, 0);
// Disable write access to PCI header
RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, ~BIT0, 0);
}
/**
* sataInitAfterPciEnum - Config SATA controller after PCI emulation
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID
sataInitAfterPciEnum (
IN AMDSBCFG* pConfig
)
{
UINT32 ddAndMask;
UINT32 ddOrMask;
UINT32 ddBar5;
UINT8 dbVar;
UINT8 dbPortNum;
UINT8 dbEfuse;
UINT8 dbPortMode;
UINT16 SataPortMode;
UINT8 cimSataAggrLinkPmCap;
UINT8 cimSataPortMultCap;
UINT8 cimSataPscCap;
UINT8 cimSataSscCap;
UINT8 cimSataFisBasedSwitching;
UINT8 cimSataCccSupport;
cimSataAggrLinkPmCap = (UINT8) pConfig->SataAggrLinkPmCap;
cimSataPortMultCap = (UINT8) pConfig->SataPortMultCap;
cimSataPscCap = (UINT8) pConfig->SataPscCap;
cimSataSscCap = (UINT8) pConfig->SataSscCap;
cimSataFisBasedSwitching = (UINT8) pConfig->SataFisBasedSwitching;
cimSataCccSupport = (UINT8) pConfig->SataCccSupport;
#if SB_CIMx_PARAMETER == 0
cimSataAggrLinkPmCap = cimSataAggrLinkPmCapDefault;
cimSataPortMultCap = cimSataPortMultCapDefault;
cimSataPscCap = cimSataPscCapDefault;
cimSataSscCap = cimSataSscCapDefault;
cimSataFisBasedSwitching = cimSataFisBasedSwitchingDefault;
cimSataCccSupport = cimSataCccSupportDefault;
#endif
ddAndMask = 0;
ddOrMask = 0;
ddBar5 = 0;
if ( pConfig->SATAMODE.SataMode.SataController == 0 ) {
return; //return if SATA controller is disabled.
}
//Enable write access to pci header, pm capabilities
RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, 0xFF, BIT0);
//Disable AHCI Prefetch function
RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 2), AccWidthUint8 | S3_SAVE, 0x7F, BIT7);
sataBar5setting (pConfig, &ddBar5);
ReadPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG04), AccWidthUint8, &dbVar);
RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG04), AccWidthUint8,0xFF, 0x03); //memory and io access enable
dbEfuse = SATA_FIS_BASE_EFUSE_LOC;
getEfuseStatus (&dbEfuse);
if ( !cimSataPortMultCap ) {
ddAndMask |= BIT12;
}
if ( cimSataAggrLinkPmCap ) {
ddOrMask |= BIT11;
} else {
ddAndMask |= BIT11;
}
if ( cimSataPscCap ) {
ddOrMask |= BIT1;
}
if ( cimSataSscCap ) {
ddOrMask |= BIT26;
}
if ( cimSataFisBasedSwitching ) {
if (dbEfuse & BIT1) {
ddAndMask |= BIT10;
} else {
ddOrMask |= BIT10;
}
} else {
ddAndMask |= BIT10;
}
// RPR 8.10 Disabling CCC (Command Completion Coalescing) support.
if ( cimSataCccSupport ) {
ddOrMask |= BIT19;
} else {
ddAndMask |= BIT19;
}
RWMEM ((ddBar5 + SB_SATA_BAR5_REGFC), AccWidthUint32 | S3_SAVE, ~ddAndMask, ddOrMask);
// SATA ESP port setting
// These config bits are set for SATA driver to identify which ports are external SATA ports and need to
// support hotplug. If a port is set as an external SATA port and need to support hotplug, then driver will
// not enable power management (HIPM & DIPM) for these ports.
if ( pConfig->SataEspPort != 0 ) {
RWMEM ((ddBar5 + SB_SATA_BAR5_REGF8), AccWidthUint32 | S3_SAVE, ~(pConfig->SataEspPort), 0);
RWMEM ((ddBar5 + SB_SATA_BAR5_REGF8), AccWidthUint32 | S3_SAVE, ~(BIT12 + BIT13 + BIT14 + BIT15 + BIT16 + BIT17 + BIT5 + BIT4 + BIT3 + BIT2 + BIT1 + BIT0), (pConfig->SataEspPort << 12));
// RPR 8.7 External SATA Port Indication Registers
// If any of the ports was programmed as an external port, HCAP.SXS should also be set
RWMEM ((ddBar5 + SB_SATA_BAR5_REGFC), AccWidthUint32 | S3_SAVE, ~(BIT20), BIT20);
} else {
// RPR 8.7 External SATA Port Indication Registers
// If any of the ports was programmed as an external port, HCAP.SXS should also be set (Clear for no ESP port)
RWMEM ((ddBar5 + SB_SATA_BAR5_REGF8), AccWidthUint32 | S3_SAVE, ~(BIT5 + BIT4 + BIT3 + BIT2 + BIT1 + BIT0), 0x00);
RWMEM ((ddBar5 + SB_SATA_BAR5_REGFC), AccWidthUint32 | S3_SAVE, ~(BIT20), 0x00);
}
if ( cimSataFisBasedSwitching ) {
if (dbEfuse & BIT1) {
RWMEM ((ddBar5 + SB_SATA_BAR5_REGF8), AccWidthUint32 | S3_SAVE, ~(BIT22 + BIT23 + BIT24 + BIT25 + BIT26 + BIT27), 0x00);
} else {
RWMEM ((ddBar5 + SB_SATA_BAR5_REGF8), AccWidthUint32 | S3_SAVE, ~(BIT22 + BIT23 + BIT24 + BIT25 + BIT26 + BIT27), (BIT22 + BIT23 + BIT24 + BIT25 + BIT26 + BIT27));
}
} else {
RWMEM ((ddBar5 + SB_SATA_BAR5_REGF8), AccWidthUint32 | S3_SAVE, ~(BIT22 + BIT23 + BIT24 + BIT25 + BIT26 + BIT27), 0x00);
}
// Disabled SATA MSI and D3 Power State capability
// RPR 8.13 SATA MSI and D3 Power State Capability
RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG34), AccWidthUint8 | S3_SAVE, 0, 0x70);
if (((pConfig->SataClass) != NATIVE_IDE_MODE) && ((pConfig->SataClass) != LEGACY_IDE_MODE)) {
// RIAD or AHCI
if ((pConfig->SATAMODE.SataMode.SataIdeCombinedMode) == DISABLED) {
RWMEM ((ddBar5 + SB_SATA_BAR5_REG00), AccWidthUint8 | S3_SAVE, ~(BIT2 + BIT1 + BIT0), BIT2 + BIT0);
RWMEM ((ddBar5 + SB_SATA_BAR5_REG0C), AccWidthUint8 | S3_SAVE, 0xC0, 0x3F);
// RPR 8.10 Disabling CCC (Command Completion Coalescing) support.
// 8 messages
RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG50 + 2), AccWidthUint8, ~(BIT3 + BIT2 + BIT1), BIT2 + BIT1);
} else {
// RPR 8.10 Disabling CCC (Command Completion Coalescing) support.
if ( pConfig->SataCccSupport ) {
// 8 messages
RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG50 + 2), AccWidthUint8, ~(BIT3 + BIT2 + BIT1), BIT2 + BIT1);
} else {
// 4 messages
RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG50 + 2), AccWidthUint8, ~(BIT3 + BIT2 + BIT1), BIT2);
}
}
}
if ( pConfig->BIOSOSHandoff == 1 ) {
RWMEM ((ddBar5 + SB_SATA_BAR5_REG24), AccWidthUint8 | S3_SAVE, ~BIT0, BIT0);
} else {
RWMEM ((ddBar5 + SB_SATA_BAR5_REG24), AccWidthUint8 | S3_SAVE, ~BIT0, 0x00);
}
SataPortMode = (UINT16)pConfig->SataPortMode;
dbPortNum = 0;
while ( dbPortNum < 6 ) {
dbPortMode = (UINT8) (SataPortMode & 3);
if ( (dbPortMode == BIT0) || (dbPortMode == BIT1) ) {
if ( dbPortMode == BIT0 ) {
// set GEN 1
RWMEM (ddBar5 + SB_SATA_BAR5_REG12C + dbPortNum * 0x80, AccWidthUint8, 0x0F, 0x10);
}
if ( dbPortMode == BIT1 ) {
// set GEN2 (default is GEN3)
RWMEM (ddBar5 + SB_SATA_BAR5_REG12C + dbPortNum * 0x80, AccWidthUint8, 0x0F, 0x20);
}
RWMEM (ddBar5 + SB_SATA_BAR5_REG12C + dbPortNum * 0x80, AccWidthUint8, 0xFF, 0x01);
}
SataPortMode >>= 2;
dbPortNum ++;
}
SbStall (1000);
SataPortMode = (UINT16)pConfig->SataPortMode;
dbPortNum = 0;
while ( dbPortNum < 6 ) {
dbPortMode = (UINT8) (SataPortMode & 3);
if ( (dbPortMode == BIT0) || (dbPortMode == BIT1) ) {
RWMEM (ddBar5 + SB_SATA_BAR5_REG12C + dbPortNum * 0x80, AccWidthUint8, 0xFE, 0x00);
}
dbPortNum ++;
SataPortMode >>= 2;
}
WritePCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG04), AccWidthUint8, &dbVar);
//Disable write access to pci header, pm capabilities
RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, ~BIT0, 0);
}
/**
* sataInitMidPost - Config SATA controller in Middle POST.
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID
sataInitMidPost (
IN AMDSBCFG* pConfig
)
{
UINT32 ddBar5;
sataBar5setting (pConfig, &ddBar5);
//If this is not S3 resume and also if SATA set to one of IDE mode, them implement drive detection workaround.
if ( ! (pConfig->S3Resume) && ( ((pConfig->SataClass) != AHCI_MODE) && ((pConfig->SataClass) != RAID_MODE) ) ) {
sataDriveDetection (pConfig, &ddBar5);
}
}
/**
* sataDriveDetection - Sata drive detection
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
* @param[in] *pBar5 Sata BAR5 base address.
*
*/
VOID
sataDriveDetection (
IN AMDSBCFG* pConfig,
IN UINT32 *pBar5
)
{
UINT32 ddVar0;
UINT8 dbPortNum;
UINT8 dbVar0;
UINT16 dwIoBase;
UINT16 dwVar0;
if ( (pConfig->SataClass == NATIVE_IDE_MODE) || (pConfig->SataClass == LEGACY_IDE_MODE) || (pConfig->SataClass == IDE_TO_AHCI_MODE) ) {
for ( dbPortNum = 0; dbPortNum < 4; dbPortNum++ ) {
ReadMEM (*pBar5 + SB_SATA_BAR5_REG128 + dbPortNum * 0x80, AccWidthUint32, &ddVar0);
if ( ( ddVar0 & 0x0F ) == 0x03 ) {
if ( dbPortNum & BIT0 ) {
//this port belongs to secondary channel
ReadPCI (((UINT32) (SATA_BUS_DEV_FUN << 16) + SB_SATA_REG18), AccWidthUint16, &dwIoBase);
} else {
//this port belongs to primary channel
ReadPCI (((UINT32) (SATA_BUS_DEV_FUN << 16) + SB_SATA_REG10), AccWidthUint16, &dwIoBase);
}
//if legacy ide mode, then the bar registers don't contain the correct values. So we need to hardcode them
if ( pConfig->SataClass == LEGACY_IDE_MODE ) {
dwIoBase = ( (0x170) | ((UINT16) ( (~((UINT8) (dbPortNum & BIT0) << 7)) & 0x80 )) );
}
if ( dbPortNum & BIT1 ) {
//this port is slave
dbVar0 = 0xB0;
} else {
//this port is master
dbVar0 = 0xA0;
}
dwIoBase &= 0xFFF8;
WriteIO (dwIoBase + 6, AccWidthUint8, &dbVar0);
//Wait in loop for 30s for the drive to become ready
for ( dwVar0 = 0; dwVar0 < 300000; dwVar0++ ) {
ReadIO (dwIoBase + 7, AccWidthUint8, &dbVar0);
if ( (dbVar0 & 0x88) == 0 ) {
break;
}
SbStall (100);
}
} //end of if ( ( ddVar0 & 0x0F ) == 0x03)
} //for (dbPortNum = 0; dbPortNum < 4; dbPortNum++)
} //if ( (pConfig->SataClass == NATIVE_IDE_MODE) || (pConfig->SataClass == LEGACY_IDE_MODE) || (pConfig->SataClass == IDE_TO_AHCI_MODE))
}
/**
* sataInitLatePost - Prepare SATA controller to boot to OS.
*
* - Set class ID to AHCI (if set to AHCI * Mode)
* - Enable AHCI interrupt
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID
sataInitLatePost (
IN AMDSBCFG* pConfig
)
{
UINT32 ddBar5;
UINT8 dbVar;
UINT8 dbPortNum;
//Return immediately is sata controller is not enabled
if ( pConfig->SATAMODE.SataMode.SataController == 0 ) {
return;
}
//Enable write access to pci header, pm capabilities
RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, 0xff, BIT0);
// if ((pConfig->SATAMODE.SataMode.SataIdeCombinedMode) == DISABLED) {
RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 1), AccWidthUint8 | S3_SAVE, ~BIT7, BIT7);
// }
sataBar5setting (pConfig, &ddBar5);
ReadPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG04), AccWidthUint8, &dbVar);
//Enable memory and io access
RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG04), AccWidthUint8, 0xFF, 0x03);
shutdownUnconnectedSataPortClock (pConfig, ddBar5);
if (( pConfig->SataClass == IDE_TO_AHCI_MODE) || ( pConfig->SataClass == IDE_TO_AHCI_MODE_4394 )) {
//program the AHCI class code
RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG08), AccWidthUint32 | S3_SAVE, 0, 0x01060100);
//Set interrupt enable bit
RWMEM ((ddBar5 + 0x04), AccWidthUint8, (UINT32)~0, BIT1);
//program the correct device id for AHCI mode
RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG02), AccWidthUint16 | S3_SAVE, 0, 0x4391);
}
if (( pConfig->SataClass == AHCI_MODE_4394 ) || ( pConfig->SataClass == IDE_TO_AHCI_MODE_4394 )) {
//program the correct device id for AHCI 4394 mode
RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG02), AccWidthUint16 | S3_SAVE, 0, 0x4394);
}
//Clear error status ?? only 4 port
RWMEM ((ddBar5 + SB_SATA_BAR5_REG130), AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, 0xFFFFFFFF);
RWMEM ((ddBar5 + SB_SATA_BAR5_REG1B0), AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, 0xFFFFFFFF);
RWMEM ((ddBar5 + SB_SATA_BAR5_REG230), AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, 0xFFFFFFFF);
RWMEM ((ddBar5 + SB_SATA_BAR5_REG2B0), AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, 0xFFFFFFFF);
RWMEM ((ddBar5 + SB_SATA_BAR5_REG330), AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, 0xFFFFFFFF);
RWMEM ((ddBar5 + SB_SATA_BAR5_REG3B0), AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, 0xFFFFFFFF);
//Restore memory and io access bits
WritePCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG04), AccWidthUint8, &dbVar );
//Disable write access to pci header and pm capabilities
RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, ~BIT0, 0);
for ( dbPortNum = 0; dbPortNum < 6; dbPortNum++ ) {
RWMEM ((ddBar5 + 0x110 + (dbPortNum * 0x80)), AccWidthUint32, 0xFFFFFFFF, 0x00);
}
}

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/*
*****************************************************************************
*
* This file is part of the coreboot project.
*
* Copyright (C) 2010 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
* ***************************************************************************
*
*/
//AMD Library Routines (AMDLIB.C)
UINT8 getNumberOfCpuCores (OUT VOID);
UINT32 readAlink (IN UINT32 Index);
VOID writeAlink (IN UINT32 Index, IN UINT32 Data);
VOID rwAlink (IN UINT32 Index, IN UINT32 AndMask, IN UINT32 OrMask);
//AMD Library Routines (LEGACY.C)
UINT32 GetFixUp (OUT VOID);
//AMD Library Routines (IOLIB.C)
VOID ReadIO (IN UINT16 Address, IN UINT8 OpFlag, IN VOID *Value);
VOID WriteIO (IN UINT16 Address, IN UINT8 OpFlag, IN VOID *Value);
VOID RWIO (IN UINT16 Address, IN UINT8 OpFlag, IN UINT32 Mask, IN UINT32 Data);
//AMD Library Routines (MEMLIB.C)
VOID ReadMEM (IN UINT32 Address, IN UINT8 OpFlag, IN VOID* Value);
VOID WriteMEM (IN UINT32 Address, IN UINT8 OpFlag, IN VOID* Value);
VOID RWMEM (IN UINT32 Address, IN UINT8 OpFlag, IN UINT32 Mask, IN UINT32 Data);
//AMD Library Routines (PCILIB.C)
VOID ReadPCI (IN UINT32 Address, IN UINT8 OpFlag, IN VOID *Value);
VOID WritePCI (IN UINT32 Address, IN UINT8 OpFlag, IN VOID *Value);
VOID RWPCI (IN UINT32 Address, IN UINT8 OpFlag, IN UINT32 Mask, IN UINT32 Data);
//AMD Library Routines (SBPELIB.C)
/**
* Read Southbridge Revision ID cie Base
*
*
* @retval 0xXXXXXXXX Revision ID
*
*/
UINT8 getRevisionID (OUT VOID);
/**
* programPciByteTable - Program PCI register by table (8 bits data)
*
*
*
* @param[in] pPciByteTable - Table data pointer
* @param[in] dwTableSize - Table length
*
*/
VOID programPciByteTable (IN REG8MASK* pPciByteTable, IN UINT16 dwTableSize);
/**
* programSbAcpiMmioTbl - Program SB ACPI MMIO register by table (8 bits data)
*
*
*
* @param[in] pAcpiTbl - Table data pointer
*
*/
VOID programSbAcpiMmioTbl (IN AcpiRegWrite *pAcpiTbl);
/**
* getChipSysMode - Get Chip status
*
*
* @param[in] Value - Return Chip strap status
* StrapStatus [15.0] - SB800 chip Strap Status
* @li <b>0001</b> - Not USED FWH
* @li <b>0002</b> - Not USED LPC ROM
* @li <b>0004</b> - EC enabled
* @li <b>0008</b> - Reserved
* @li <b>0010</b> - Internal Clock mode
*
*/
VOID getChipSysMode (IN VOID* Value);
/**
* Read Southbridge CIMx configuration structure pointer
*
*
*
* @retval 0xXXXXXXXX CIMx configuration structure pointer.
*
*/
AMDSBCFG* getConfigPointer (OUT VOID);
//AMD Library Routines (PMIOLIB.C)
/**
* Read PMIO
*
*
*
* @param[in] Address - PMIO Offset value
* @param[in] OpFlag - Access sizes
* @param[in] Value - Read Data Buffer
*
*/
VOID ReadPMIO (IN UINT8 Address, IN UINT8 OpFlag, IN VOID* Value);
/**
* Write PMIO
*
*
*
* @param[in] Address - PMIO Offset value
* @param[in] OpFlag - Access sizes
* @param[in] Value - Write Data Buffer
*
*/
VOID WritePMIO (IN UINT8 Address, IN UINT8 OpFlag, IN VOID* Value);
/**
* RWPMIO - Read/Write PMIO
*
*
*
* @param[in] Address - PMIO Offset value
* @param[in] OpFlag - Access sizes
* @param[in] AndMask - Data And Mask 32 bits
* @param[in] OrMask - Data OR Mask 32 bits
*
*/
VOID RWPMIO (IN UINT8 Address, IN UINT8 OpFlag, IN UINT32 AndMask, IN UINT32 OrMask);
//AMD Library Routines (PMIO2LIB.C)
/**
* Read PMIO2
*
*
*
* @param[in] Address - PMIO2 Offset value
* @param[in] OpFlag - Access sizes
* @param[in] Value - Read Data Buffer
*
*/
VOID ReadPMIO2 (IN UINT8 Address, IN UINT8 OpFlag, IN VOID* Value);
/**
* Write PMIO 2
*
*
*
* @param[in] Address - PMIO2 Offset value
* @param[in] OpFlag - Access sizes
* @param[in] Value - Write Data Buffer
*
*/
VOID WritePMIO2 (IN UINT8 Address, IN UINT8 OpFlag, IN VOID* Value);
/**
* RWPMIO2 - Read/Write PMIO2
*
*
*
* @param[in] Address - PMIO2 Offset value
* @param[in] OpFlag - Access sizes
* @param[in] AndMask - Data And Mask 32 bits
* @param[in] OrMask - Data OR Mask 32 bits
*
*/
VOID RWPMIO2 (IN UINT8 Address, IN UINT8 OpFlag, IN UINT32 AndMask, IN UINT32 OrMask);
//AMD Library Routines (ECLIB.C)
// ECLIB Routines
// #ifndef NO_EC_SUPPORT
/**
* EnterEcConfig - Force EC into Config mode
*
*
*
*
*/
VOID EnterEcConfig (VOID);
/**
* ExitEcConfig - Force EC exit Config mode
*
*
*
*
*/
VOID ExitEcConfig (VOID);
/**
* ReadEC8 - Read EC register data
*
*
*
* @param[in] Address - EC Register Offset Value
* @param[in] Value - Read Data Buffer
*
*/
VOID ReadEC8 (IN UINT8 Address, IN UINT8* Value);
/**
* WriteEC8 - Write date into EC register
*
*
*
* @param[in] Address - EC Register Offset Value
* @param[in] Value - Write Data Buffer
*
*/
VOID WriteEC8 (IN UINT8 Address, IN UINT8* Value);
/**
* RWEC8 - Read/Write EC register
*
*
*
* @param[in] Address - EC Register Offset Value
* @param[in] AndMask - Data And Mask 8 bits
* @param[in] OrMask - Data OR Mask 8 bits
*
*/
VOID RWEC8 (IN UINT8 Address, IN UINT8 AndMask, IN UINT8 OrMask);
/**
* IsZoneFuncEnable - check every zone support function with BitMap from user define
*
*/
BOOLEAN IsZoneFuncEnable ( UINT16 Flag, UINT8 func, UINT8 Zone);
VOID sbECfancontrolservice (IN AMDSBCFG* pConfig);
VOID SBIMCFanInitializeS3 (VOID);
VOID GetSbAcpiMmioBase (OUT UINT32* AcpiMmioBase);
VOID GetSbAcpiPmBase (OUT UINT16* AcpiPmBase);
// #endif

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/**
* @file
*
* SB Initialization.
*
* Init IOAPIC/IOMMU/Misc NB features.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: CIMx-SB
* @e sub-project:
* @e \$Revision:$ @e \$Date:$
*
*/
/*
*****************************************************************************
*
* This file is part of the coreboot project.
*
* Copyright (C) 2010 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
* ***************************************************************************
*
*/
#include "SBPLATFORM.h"
#ifndef B1_IMAGE
/*----------------------------------------------------------------------------------------*/
/**
* sbBeforePciInit - Config Southbridge before PCI emulation
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID
sbBeforePciInit (
IN AMDSBCFG* pConfig
)
{
commonInitEarlyBoot (pConfig);
commonInitEarlyPost (pConfig);
#ifndef NO_EC_SUPPORT
ecInitBeforePciEnum (pConfig);
#endif
usbInitBeforePciEnum (pConfig); // USB POST TIME Only
sataInitBeforePciEnum (pConfig); // Init SATA class code and PHY
gecInitBeforePciEnum (pConfig); // Init GEC
azaliaInitBeforePciEnum (pConfig); // Detect and configure High Definition Audio
sbPcieGppEarlyInit (pConfig); // Gpp port init
abSpecialSetBeforePciEnum (pConfig);
usbDesertPll (pConfig);
}
/**
* sbAfterPciInit - Config Southbridge after PCI emulation
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID
sbAfterPciInit (
IN AMDSBCFG* pConfig
)
{
usbInitAfterPciInit (pConfig); // Init USB MMIO
sataInitAfterPciEnum (pConfig); // SATA port enumeration
gecInitAfterPciEnum (pConfig);
azaliaInitAfterPciEnum (pConfig); // Detect and configure High Definition Audio
#ifndef NO_HWM_SUPPORT
hwmInit (pConfig);
#endif
}
/**
* sbMidPostInit - Config Southbridge during middle of POST
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID
sbMidPostInit (
IN AMDSBCFG* pConfig
)
{
sataInitMidPost (pConfig);
}
/*----------------------------------------------------------------------------------------*/
/**
* sbLatePost - Prepare Southbridge to boot to OS.
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID
sbLatePost (
IN AMDSBCFG* pConfig
)
{
// UINT16 dwVar;
BUILDPARAM *pStaticOptions;
pStaticOptions = &(pConfig->BuildParameters);
commonInitLateBoot (pConfig);
sataInitLatePost (pConfig);
gecInitLatePost (pConfig);
hpetInit (pConfig, pStaticOptions); // SB Configure HPET base and enable bit
#ifndef NO_EC_SUPPORT
ecInitLatePost (pConfig);
#endif
sbPcieGppLateInit (pConfig);
}
/*----------------------------------------------------------------------------------------*/
/**
* sbBeforePciRestoreInit - Config Southbridge before ACPI S3 resume PCI config device restore
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID
sbBeforePciRestoreInit (
IN AMDSBCFG* pConfig
)
{
pConfig->S3Resume = 1;
commonInitEarlyBoot (pConfig); // set /SMBUS/ACPI/IDE/LPC/PCIB
abLinkInitBeforePciEnum (pConfig); // Set ABCFG registers
usbInitBeforePciEnum (pConfig); // USB POST TIME Only
sataInitBeforePciEnum (pConfig);
gecInitBeforePciEnum (pConfig); // Init GEC
azaliaInitBeforePciEnum (pConfig); // Detect and configure High Definition Audio
sbPcieGppEarlyInit (pConfig); // Gpp port init
abSpecialSetBeforePciEnum (pConfig);
}
/*----------------------------------------------------------------------------------------*/
/**
* sbAfterPciRestoreInit - Config Southbridge after ACPI S3 resume PCI config device restore
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID
sbAfterPciRestoreInit (
IN AMDSBCFG* pConfig
)
{
BUILDPARAM *pStaticOptions;
pConfig->S3Resume = 1;
usbSetPllDuringS3 (pConfig);
pStaticOptions = &(pConfig->BuildParameters);
commonInitLateBoot (pConfig);
sataInitAfterPciEnum (pConfig);
gecInitAfterPciEnum (pConfig);
azaliaInitAfterPciEnum (pConfig); // Detect and configure High Definition Audio
hpetInit (pConfig, pStaticOptions); // SB Configure HPET base and enable bit
sataInitLatePost (pConfig);
c3PopupSetting (pConfig);
#ifndef NO_HWM_SUPPORT
SBIMCFanInitializeS3 ();
#endif
}
/*----------------------------------------------------------------------------------------*/
/**
* sbSmmAcpiOn - Config Southbridge during ACPI_ON
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID
sbSmmAcpiOn (
IN AMDSBCFG* pConfig
)
{
// Commented the following code since we need to leave the IRQ1/12 filtering enabled always as per latest
// recommendation in RPR. This is required to fix the keyboard stuck issue when playing games under Windows
AMDSBCFG* pTmp; //lx-dummy for /W4 build
pTmp = pConfig;
// Disable Power Button SMI
RWMEM (ACPI_MMIO_BASE + SMI_BASE + SB_SMI_REGB2, AccWidthUint8, ~(BIT4 + BIT5), 0);
RWMEM (ACPI_MMIO_BASE + SMI_BASE + SB_SMI_REGAC, AccWidthUint8, ~(BIT6 + BIT7), 0);
}
#endif
/*----------------------------------------------------------------------------------------*/
/**
* Call Back routine.
*
*
*
* @param[in] Func Callback ID.
* @param[in] Data Callback specific data.
* @param[in] pConfig Southbridge configuration structure pointer.
*/
UINTN
CallBackToOEM (
IN UINT32 Func,
IN UINT32 Data,
IN AMDSBCFG* pConfig
)
{
UINT32 Result;
Result = 0;
if ( pConfig->StdHeader.CALLBACK.CalloutPtr == NULL ) return Result;
Result = (pConfig->StdHeader.CALLBACK.CalloutPtr) ( Func, Data, pConfig);
return Result;
}

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/**
* @file
*
* Southbridge IO access common routine
*
*
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: CIMx-SB
* @e sub-project:
* @e \$Revision:$ @e \$Date:$
*
*/
/*
*****************************************************************************
*
* This file is part of the coreboot project.
*
* Copyright (C) 2010 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
* ***************************************************************************
*
*/
#include "SBPLATFORM.h"
/**
* Read Southbridge Revision ID cie Base
*
*
* @retval 0xXXXXXXXX Revision ID
*
*/
UINT8
getRevisionID (
OUT VOID
)
{
UINT8 dbVar0;
ReadPCI (((SMBUS_BUS_DEV_FUN << 16) + SB_CFG_REG08), AccWidthUint8, &dbVar0);
return dbVar0;
}
/*----------------------------------------------------------------------------------------*/
/**
* programPciByteTable - Program PCI register by table (8 bits data)
*
*
*
* @param[in] pPciByteTable - Table data pointer
* @param[in] dwTableSize - Table length
*
*/
VOID
programPciByteTable (
IN REG8MASK* pPciByteTable,
IN UINT16 dwTableSize
)
{
UINT8 i;
UINT8 dbBusNo;
UINT8 dbDevFnNo;
UINT32 ddBDFR;
dbBusNo = pPciByteTable->bRegIndex;
dbDevFnNo = pPciByteTable->bANDMask;
pPciByteTable++;
for ( i = 1; i < dwTableSize; i++ ) {
if ( (pPciByteTable->bRegIndex == 0xFF) && (pPciByteTable->bANDMask == 0xFF) && (pPciByteTable->bORMask == 0xFF) ) {
pPciByteTable++;
dbBusNo = pPciByteTable->bRegIndex;
dbDevFnNo = pPciByteTable->bANDMask;
pPciByteTable++;
i++;
} else {
ddBDFR = (dbBusNo << 24) + (dbDevFnNo << 16) + (pPciByteTable->bRegIndex) ;
RWPCI (ddBDFR, AccWidthUint8 | S3_SAVE, pPciByteTable->bANDMask, pPciByteTable->bORMask);
pPciByteTable++;
}
}
}
/*----------------------------------------------------------------------------------------*/
/**
* programSbAcpiMmioTbl - Program SB ACPI MMIO register by table (8 bits data)
*
*
*
* @param[in] pAcpiTbl - Table data pointer
*
*/
VOID
programSbAcpiMmioTbl (
IN AcpiRegWrite *pAcpiTbl
)
{
UINT8 i;
UINT32 ddtempVar;
if (pAcpiTbl != NULL) {
for ( i = 1; pAcpiTbl->MmioBase < 0xf0; i++ ) {
ddtempVar = 0xFED80000 | (pAcpiTbl->MmioBase) << 8 | pAcpiTbl->MmioReg;
RWMEM (ddtempVar, AccWidthUint8, ((pAcpiTbl->DataANDMask) | 0xFFFFFF00), pAcpiTbl->DataOrMask);
pAcpiTbl++;
}
}
}
/**
* getChipSysMode - Get Chip status
*
*
* @param[in] Value - Return Chip strap status
* StrapStatus [15.0] - SB800 chip Strap Status
* @li <b>0001</b> - Not USED FWH
* @li <b>0002</b> - Not USED LPC ROM
* @li <b>0004</b> - EC enabled
* @li <b>0008</b> - Reserved
* @li <b>0010</b> - Internal Clock mode
*
*/
VOID
getChipSysMode (
IN VOID* Value
)
{
ReadMEM (ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG80, AccWidthUint8, Value);
}
/*----------------------------------------------------------------------------------------*/
/**
* Read Southbridge CIMx configuration structure pointer
*
*
*
* @retval 0xXXXXXXXX CIMx configuration structure pointer.
*
*/
AMDSBCFG*
getConfigPointer (
OUT VOID
)
{
UINT8 dbReg;
UINT8 dbValue;
UINT8 i;
UINT32 ddValue;
ddValue = 0;
dbReg = SB_ECMOS_REG08;
for ( i = 0; i <= 3; i++ ) {
WriteIO (SB_IOMAP_REG72, AccWidthUint8, &dbReg);
ReadIO (SB_IOMAP_REG73, AccWidthUint8, &dbValue);
ddValue |= (dbValue << (i * 8));
dbReg++;
}
return ( (AMDSBCFG*) (UINTN)ddValue);
}
/**
* getEfuseStatue - Get Efuse status
*
*
* @param[in] Value - Return Chip strap status
*
*/
VOID
getEfuseStatus (
IN VOID* Value
)
{
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC8, AccWidthUint8, ~BIT5, BIT5);
WriteMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD8, AccWidthUint8, Value);
ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD8 + 1, AccWidthUint8, Value);
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC8, AccWidthUint8, ~BIT5, 0);
}

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/**
* @file
*
* Southbridge Init during POWER-ON
*
* Prepare Southbridge environment during power on stage.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: CIMx-SB
* @e sub-project:
* @e \$Revision:$ @e \$Date:$
*
*/
/*
*****************************************************************************
*
* This file is part of the coreboot project.
*
* Copyright (C) 2010 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
* ***************************************************************************
*
*/
#include "SBPLATFORM.h"
/**
* sbPorInitPciTable - PCI device registers initial during the power on stage.
*/
const static REG8MASK sbPorInitPciTable[] =
{
// SATA device
{0x00, SATA_BUS_DEV_FUN, 0},
{SB_SATA_REG84 + 3, ~BIT2, 0},
{SB_SATA_REG84 + 1, ~(BIT4 + BIT5), BIT4 + BIT5},
{SB_SATA_REGA0, ~(BIT2 + BIT3 + BIT4 + BIT5 + BIT6), BIT2 + BIT3 + BIT4 + BIT5},
{0xFF, 0xFF, 0xFF},
// LPC Device (Bus 0, Dev 20, Func 3)
{0x00, LPC_BUS_DEV_FUN, 0},
{SB_LPC_REG48, 0x00, BIT0 + BIT1 + BIT2},
{SB_LPC_REG7C, 0x00, BIT0 + BIT2},
{SB_LPC_REGBB, 0xFF, BIT3 + BIT4 + BIT5},
// A12 set 0xBB [5:3] = 111 to improve SPI timing margin.
// A12 Set 0xBA [6:5] = 11 improve SPI timing margin. (SPI Prefetch enhancement)
{SB_LPC_REGBB, 0xBE, BIT0 + BIT3 + BIT4 + BIT5},
{SB_LPC_REGBA, 0x9F, BIT5 + BIT6},
{0xFF, 0xFF, 0xFF},
// P2P Bridge (Bus 0, Dev 20, Func 4)
{0x00, PCIB_BUS_DEV_FUN, 0},
{SB_PCIB_REG4B, 0xFF, BIT6 + BIT7 + BIT4},
// Enable IO but not allocate any IO range. This is for post code display on debug port behind P2P bridge.
{SB_PCIB_REG1C, 0x00, 0xF0},
{SB_PCIB_REG1D, 0x00, 0x00},
{SB_PCIB_REG04, 0x00, 0x21},
{SB_PCIB_REG40, 0xDF, 0x20},
{SB_PCIB_REG50, 0x02, 0x01},
{0xFF, 0xFF, 0xFF},
};
/**
* sbPmioPorInitTable - Southbridge ACPI MMIO initial during the power on stage.
*/
const static AcpiRegWrite sbPmioPorInitTable[] =
{
{PMIO_BASE >> 8, SB_PMIOA_REG5D, 0x00, BIT0},
{PMIO_BASE >> 8, SB_PMIOA_REGD2, 0xCF, BIT4 + BIT5},
{SMBUS_BASE >> 8, SB_SMBUS_REG12, 0x00, BIT0},
{PMIO_BASE >> 8, SB_PMIOA_REG28, 0xFF, BIT0},
{PMIO_BASE >> 8, SB_PMIOA_REG44 + 3, 0x7F, BIT7},
{PMIO_BASE >> 8, SB_PMIOA_REG48, 0xFF, BIT0},
{PMIO_BASE >> 8, SB_PMIOA_REG00, 0xFF, 0x0E},
{PMIO_BASE >> 8, SB_PMIOA_REG00 + 2, 0xFF, 0x40},
{PMIO_BASE >> 8, SB_PMIOA_REG00 + 3, 0xFF, 0x08},
{PMIO_BASE >> 8, SB_PMIOA_REG34, 0xEF, BIT0 + BIT1},
{PMIO_BASE >> 8, SB_PMIOA_REGEC, 0xFD, BIT1},
{PMIO_BASE >> 8, SB_PMIOA_REG5B, 0xF9, BIT1 + BIT2},
{PMIO_BASE >> 8, SB_PMIOA_REG08, 0xFE, BIT2 + BIT4},
{PMIO_BASE >> 8, SB_PMIOA_REG08 + 1, 0xFF, BIT0},
{PMIO_BASE >> 8, SB_PMIOA_REG54, 0x00, BIT4 + BIT7},
{PMIO_BASE >> 8, SB_PMIOA_REG04 + 3, 0xFD, BIT1},
{PMIO_BASE >> 8, SB_PMIOA_REG74, 0xF6, BIT0 + BIT3},
{PMIO_BASE >> 8, SB_PMIOA_REGF0, ~BIT2, 0x00},
// RPR GEC I/O Termination Setting
// PM_Reg 0xF6 = Power-on default setting
// PM_Reg 0xF7 = Power-on default setting
// PM_Reg 0xF8 = 0x6C
// PM_Reg 0xF9 = 0x21
// PM_Reg 0xFA = 0x00 SB800 A12 GEC I/O Pad settings for 3.3V CMOS
{PMIO_BASE >> 8, SB_PMIOA_REGF8, 0x00, 0x6C},
{PMIO_BASE >> 8, SB_PMIOA_REGF8 + 1, 0x00, 0x27},
{PMIO_BASE >> 8, SB_PMIOA_REGF8 + 2, 0x00, 0x00},
{PMIO_BASE >> 8, SB_PMIOA_REGC4, 0xFE, 0x14},
{PMIO_BASE >> 8, SB_PMIOA_REGC0 + 2, 0xBF, 0x40},
{PMIO_BASE >> 8, SB_PMIOA_REGBE, 0xDF, BIT5},//ENH210907 SB800: request to no longer clear kb_pcirst_en (bit 1) of PM_Reg BEh per the RPR
{0xFF, 0xFF, 0xFF, 0xFF},
};
/**
* sbPowerOnInit - Config Southbridge during power on stage.
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID
sbPowerOnInit (
IN AMDSBCFG* pConfig
)
{
UINT8 dbPortStatus;
UINT8 dbSysConfig;
UINT32 abValue;
UINT8 dbValue;
UINT8 dbEfuse;
UINT8 dbCg2WR;
UINT8 dbCg1Pll;
UINT8 cimNbSbGen2;
UINT8 cimSataMode;
UINT8 cimSpiFastReadEnable;
UINT8 cimSpiFastReadSpeed;
UINT8 SataPortNum;
cimNbSbGen2 = pConfig->NbSbGen2;
cimSataMode = pConfig->SATAMODE.SataModeReg;
// Adding Fast Read Function support
if (pConfig->BuildParameters.SpiFastReadEnable != NULL ) {
cimSpiFastReadEnable = (UINT8) pConfig->BuildParameters.SpiFastReadEnable;
} else {
cimSpiFastReadEnable = cimSpiFastReadEnableDefault;
}
cimSpiFastReadSpeed = (UINT8) pConfig->BuildParameters.SpiFastReadSpeed;
#if SB_CIMx_PARAMETER == 0
cimNbSbGen2 = cimNbSbGen2Default;
cimSataMode = (UINT8) ((cimSataMode & 0xFB) | cimSataSetMaxGen2Default);
cimSataMode = (UINT8) ((cimSataMode & 0x0F) | (cimSATARefClkSelDefault + cimSATARefDivSelDefault));
cimSpiFastReadEnable = cimSpiFastReadEnableDefault;
cimSpiFastReadSpeed = cimSpiFastReadSpeedDefault;
#endif
// SB800 Only Enabled (Mmio_mem_enablr) // Default value is correct
RWPMIO (SB_PMIOA_REG24, AccWidthUint8, 0xFF, BIT0);
// Set A-Link bridge access address. This address is set at device 14h, function 0,
// register 0f0h. This is an I/O address. The I/O address must be on 16-byte boundary.
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGE0, AccWidthUint32, 00, ALINK_ACCESS_INDEX);
writeAlink (0x80000004, 0x04); // RPR 4.2 Enable SB800 to issue memory read/write requests in the upstream direction
abValue = readAlink (SB_ABCFG_REG9C | (UINT32) (ABCFG << 29)); // RPR 4.5 Disable the credit variable in the downstream arbitration equation
abValue = abValue | BIT0;
writeAlink (SB_ABCFG_REG9C | (UINT32) (ABCFG << 29), abValue);
writeAlink (0x30, 0x10); // AXINDC 0x10[9]=1, Enabling Non-Posted memory write for K8 platform.
writeAlink (0x34, readAlink (0x34) | BIT9);
dbEfuse = FUSE_ID_EFUSE_LOC;
getEfuseStatus (&dbEfuse);
if ( dbEfuse == M1_D1_FUSE_ID ) {
dbEfuse = MINOR_ID_EFUSE_LOC;
getEfuseStatus (&dbEfuse);
if ( dbEfuse == M1_MINOR_ID ) {
// Limit ALink speed to 2.5G if Hudson-M1
cimNbSbGen2 = 0;
}
}
// Step 1:
// AXINDP_Reg 0xA4[0] = 0x1
// Step 2:
// AXCFG_Reg 0x88[3:0] = 0x2
// Step3:
// AXINDP_Reg 0xA4[18] = 0x1
if ( cimNbSbGen2 == TRUE ) {
rwAlink (SB_AX_INDXP_REGA4, 0xFFFFFFFF, BIT0);
rwAlink ((UINT32)SB_AX_CFG_REG88, 0xFFFFFFF0, 0x2);
rwAlink (SB_AX_INDXP_REGA4, 0xFFFFFFFF, BIT18);
}
// Set Build option into SB
WritePCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG64, AccWidthUint16 | S3_SAVE, &(pConfig->BuildParameters.SioPmeBaseAddress));
RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA0, AccWidthUint32 | S3_SAVE, 0x001F, (pConfig->BuildParameters.SpiRomBaseAddress));
RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG9C, AccWidthUint32 | S3_SAVE, 0, (pConfig->BuildParameters.GecShadowRomBase + 1));
// Enabled SMBUS0/SMBUS1 (ASF) Base Address
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG2C, AccWidthUint16, 06, (pConfig->BuildParameters.Smbus0BaseAddress) + BIT0); //protect BIT[2:1]
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG28, AccWidthUint16, 00, (pConfig->BuildParameters.Smbus1BaseAddress));
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG60, AccWidthUint16, 00, (pConfig->BuildParameters.AcpiPm1EvtBlkAddr));
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG62, AccWidthUint16, 00, (pConfig->BuildParameters.AcpiPm1CntBlkAddr));
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG64, AccWidthUint16, 00, (pConfig->BuildParameters.AcpiPmTmrBlkAddr));
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG66, AccWidthUint16, 00, (pConfig->BuildParameters.CpuControlBlkAddr));
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG68, AccWidthUint16, 00, (pConfig->BuildParameters.AcpiGpe0BlkAddr));
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG6A, AccWidthUint16, 00, (pConfig->BuildParameters.SmiCmdPortAddr));
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG6C, AccWidthUint16, 00, (pConfig->BuildParameters.AcpiPmaCntBlkAddr));
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG6E, AccWidthUint16, 00, (pConfig->BuildParameters.SmiCmdPortAddr) + 8);
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG48, AccWidthUint32, 00, (pConfig->BuildParameters.WatchDogTimerBase));
dbEfuse = SATA_FIS_BASE_EFUSE_LOC;
getEfuseStatus (&dbEfuse);
programSbAcpiMmioTbl ((AcpiRegWrite*) FIXUP_PTR (&sbPmioPorInitTable[0]));
SataPortNum = 0;
for ( SataPortNum = 0; SataPortNum < 0x06; SataPortNum++ ) {
RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 2), AccWidthUint8, 0xFF, 1 << SataPortNum);
SbStall (2);
RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 2), AccWidthUint8, (0xFF ^ (1 << SataPortNum)) , 0x00);
SbStall (2);
}
//The following bits must be set before enabling SPI prefetch.
// Set SPI MMio bit offset 00h[19] to 1 and offset 00h[26:24] to 111, offset 0ch[21:16] to 1, Set LPC cfg BBh[6] to 0 ( by default it is 0).
// if Ec is enable
// Maximum spi speed that can be supported by SB is 22M (SPI Mmio offset 0ch[13:12] to 10) if the rom can run at the speed.
// else
// Maximum spi speed that can be supported by SB is 33M (SPI Mmio offset 0ch[13:12] to 01 in normal mode or offset 0ch[15:14] in fast mode) if the rom can run at
// the speed.
getChipSysMode (&dbSysConfig);
if (pConfig->BuildParameters.SpiSpeed < 0x02) {
pConfig->BuildParameters.SpiSpeed = 0x01;
if (dbSysConfig & ChipSysEcEnable) pConfig->BuildParameters.SpiSpeed = 0x02;
}
if (pConfig->SbSpiSpeedSupport) {
RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG00, AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, (BIT19 + BIT24 + BIT25 + BIT26));
RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG0C, AccWidthUint32 | S3_SAVE, 0xFFC0FFFF, 1 << 16 );
RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG0C, AccWidthUint16 | S3_SAVE, ~(BIT13 + BIT12), (pConfig->BuildParameters.SpiSpeed << 12));
}
// SPI Fast Read Function
if ( cimSpiFastReadEnable ) {
RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG00, AccWidthUint32 | S3_SAVE, 0xFFFBFFFF, BIT18);
} else {
RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG00, AccWidthUint32 | S3_SAVE, 0xFFFBFFFF, 0x00);
}
if ( cimSpiFastReadSpeed ) {
RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG0C, AccWidthUint16 | S3_SAVE, ~(BIT15 + BIT14), ( cimSpiFastReadSpeed << 14));
}
//Program power on pci init table
programPciByteTable ( (REG8MASK*) FIXUP_PTR (&sbPorInitPciTable[0]), sizeof (sbPorInitPciTable) / sizeof (REG8MASK) );
programSbAcpiMmioTbl ((AcpiRegWrite *) (pConfig->OEMPROGTBL.OemProgrammingTablePtr_Ptr));
dbValue = 0x0A;
WriteIO (SB_IOMAP_REG70, AccWidthUint8, &dbValue);
ReadIO (SB_IOMAP_REG71, AccWidthUint8, &dbValue);
dbValue &= 0xEF;
WriteIO (SB_IOMAP_REG71, AccWidthUint8, &dbValue);
// Change the CG PLL multiplier to x1.1
if ( pConfig->UsbRxMode !=0 ) {
dbCg2WR = 0x00;
dbCg1Pll = 0x3A;
ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC8, AccWidthUint8, &dbCg2WR);
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD8, AccWidthUint8, 0, 0x3A);
ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD9, AccWidthUint8, &dbCg1Pll);
dbCg2WR &= BIT4;
if (( dbCg2WR == 0x00 ) && ( dbCg1Pll !=0x10 ))
{
RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x18, AccWidthUint8, 0xE1, 0x10);
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD8, AccWidthUint8, 0, 0x3A);
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD9, AccWidthUint8, 0, USB_PLL_Voltage);
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC8, AccWidthUint8, 0xEF, 0x10);
dbValue = 0x06;
WriteIO (0xCF9, AccWidthUint8, &dbValue);
} else {
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC8, AccWidthUint8, 0xEF, 0x00);
}
}
RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG6C, AccWidthUint32 | S3_SAVE, ~(pConfig->BuildParameters.BiosSize << 4), 0);
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGDA, AccWidthUint8, 0, (pConfig->SATAMODE.SataModeReg) & 0xFD );
if (dbEfuse & BIT0) {
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGDA, AccWidthUint8, 0xFB, 0x04);
}
ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGDA, AccWidthUint8, &dbPortStatus);
if ( ((dbPortStatus & 0xF0) == 0x10) ) {
RWMEM (ACPI_MMIO_BASE + MISC_BASE + SB_PMIOA_REG08, AccWidthUint8, 0, BIT5);
}
if ( pConfig->BuildParameters.LegacyFree ) {
RWPCI (((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG44), AccWidthUint32 | S3_SAVE, 00, 0x0003C000);
} else {
RWPCI (((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG44), AccWidthUint32 | S3_SAVE, 00, 0xFF03FFD5);
}
dbValue = 0x09;
WriteIO (SB_IOMAP_REGC00, AccWidthUint8, &dbValue);
ReadIO (SB_IOMAP_REGC01, AccWidthUint8, &dbValue);
if ( !pConfig->BuildParameters.EcKbd ) {
// Route SIO IRQ1/IRQ12 to USB IRQ1/IRQ12 input
dbValue = dbValue & 0xF9;
}
if ( pConfig->BuildParameters.LegacyFree ) {
// Disable IRQ1/IRQ12 filter enable for Legacy free with USB KBC emulation.
dbValue = dbValue & 0x9F;
}
// Enabled IRQ input
dbValue = dbValue | BIT4;
WriteIO (SB_IOMAP_REGC01, AccWidthUint8, &dbValue);
#ifndef NO_EC_SUPPORT
getChipSysMode (&dbPortStatus);
if ( ((dbPortStatus & ChipSysEcEnable) == 0x00) ) {
// EC is disabled by jumper setting or board config
RWPCI (((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4), AccWidthUint16 | S3_SAVE, 0xFFFE, BIT0);
} else {
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC4, AccWidthUint8, 0xF7, 0x08);
ecPowerOnInit ( pConfig);
}
#endif
ReadMEM (ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG80, AccWidthUint8, &dbValue);
if (dbValue & ChipSysIntClkGen) {
ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC4, AccWidthUint8, &dbValue);
if (dbValue & BIT2) {
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC0 + 2, AccWidthUint8, 0xDF, 0x20);
} else {
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC4, AccWidthUint8, 0xFB, 0x40);
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC0 + 2, AccWidthUint8, 0xDF, 0x20);
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC4, AccWidthUint8, 0xFB, 0x00);
}
}
// Restore GPP clock to on as it may be off during last POST when some device was disabled;
// the device can't be detected if enabled again as the values retain on S5 and warm reset.
RWMEM (ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG00, AccWidthUint32, 0xFFFFFFFF, 0xFFFFFFFF);
RWMEM (ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG04, AccWidthUint8, 0xFF, 0xFF);
// Set PMx88[5]to enable LdtStp# output to do the C3 or FidVid transation
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG88, AccWidthUint8, 0xFF, BIT5);
}

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src/vendorcode/amd/cimx/sb800/SBSUBFUN.h Normal file
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@ -0,0 +1,514 @@
/**
* @file
*
* Southbridge CIMx Function Support Define (All)
*
*
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: CIMx-SB
* @e sub-project:
* @e \$Revision:$ @e \$Date:$
*
*/
/*
*****************************************************************************
*
* This file is part of the coreboot project.
*
* Copyright (C) 2010 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
* ***************************************************************************
*
*/
// Southbridge SBMAIN Routines
/**
* Southbridge Main Function Public Function
*
*/
/**
* sbBeforePciInit - Config Southbridge before PCI emulation
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID sbBeforePciInit (IN AMDSBCFG* pConfig);
/**
* sbAfterPciInit - Config Southbridge after PCI emulation
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID sbAfterPciInit (IN AMDSBCFG* pConfig);
/**
* sbMidPostInit - Config Southbridge during middle of POST
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID sbMidPostInit (IN AMDSBCFG* pConfig);
/**
* sbLatePost - Prepare Southbridge to boot to OS.
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID sbLatePost (IN AMDSBCFG* pConfig);
/**
* sbBeforePciRestoreInit - Config Southbridge before ACPI S3 resume PCI config device restore
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID sbBeforePciRestoreInit (IN AMDSBCFG* pConfig);
/**
* sbAfterPciRestoreInit - Config Southbridge after ACPI S3 resume PCI config device restore
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID sbAfterPciRestoreInit (IN AMDSBCFG* pConfig);
/**
* sbSmmAcpiOn - Config Southbridge during ACPI_ON
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID sbSmmAcpiOn (IN AMDSBCFG* pConfig);
/**
* CallBackToOEM - Call Back routine.
*
*
*
* @param[in] Func Callback ID.
* @param[in] Data Callback specific data.
* @param[in] pConfig Southbridge configuration structure pointer.
*/
UINTN CallBackToOEM (IN UINT32 Func, IN UINT32 Data, IN AMDSBCFG* pConfig);
// Southbridge SBPOR Routines
/**
* Southbridge power-on initial Public Function
*
*/
/**
* sbPowerOnInit - Config Southbridge during power on stage.
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID sbPowerOnInit (IN AMDSBCFG* pConfig);
// Southbridge Common Routines
/**
* Southbridge Common Public Function
*
*/
/**
* commonInitEarlyBoot - Config Southbridge SMBUS/ACPI/IDE/LPC/PCIB.
*
* This settings should be done during S3 resume also
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID commonInitEarlyBoot (IN AMDSBCFG* pConfig);
/**
* commonInitEarlyPost - Config Southbridge SMBUS/ACPI/IDE/LPC/PCIB.
*
* This settings might not program during S3 resume
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID commonInitEarlyPost (IN AMDSBCFG* pConfig);
/**
* commonInitLateBoot - Prepare Southbridge register setting to boot to OS.
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID commonInitLateBoot (IN AMDSBCFG* pConfig);
/**
* abSpecialSetBeforePciEnum - Special setting ABCFG registers before PCI emulation.
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID abSpecialSetBeforePciEnum (IN AMDSBCFG* pConfig);
VOID usbSetPllDuringS3 (IN AMDSBCFG* pConfig);
VOID usbDesertPll (IN AMDSBCFG* pConfig);
/**
* hpetInit - Program Southbridge HPET function
*
* ** Eric
*
* @param[in] pConfig Southbridge configuration structure pointer.
* @param[in] pStaticOptions Platform build configuration table.
*
*/
VOID hpetInit (IN AMDSBCFG* pConfig, IN BUILDPARAM *pStaticOptions);
/**
* c3PopupSetting - Program Southbridge C state function
*
* ** Eric
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID c3PopupSetting (IN AMDSBCFG* pConfig);
/**
* FusionRelatedSetting - Program Fusion C related function
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID FusionRelatedSetting (IN AMDSBCFG* pConfig);
/**
* Southbridge Common Private Function
*
*/
/**
* abLinkInitBeforePciEnum - Set ABCFG registers before PCI emulation.
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID abLinkInitBeforePciEnum (IN AMDSBCFG* pConfig);
// Southbridge SATA Routines
/**
* Southbridge SATA Controller Public Function
*
*/
/**
* sataInitMidPost - Config SATA controller in Middle POST.
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID sataInitMidPost (IN AMDSBCFG* pConfig);
/**
* sataInitAfterPciEnum - Config SATA controller after PCI emulation
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID sataInitAfterPciEnum (IN AMDSBCFG* pConfig);
/**
* sataInitBeforePciEnum - Config SATA controller before PCI emulation
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID sataInitBeforePciEnum (IN AMDSBCFG* pConfig);
/**
* sataInitLatePost - Prepare SATA controller to boot to OS.
*
* - Set class ID to AHCI (if set to AHCI * Mode)
* - Enable AHCI interrupt
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID sataInitLatePost (IN AMDSBCFG* pConfig);
// Southbridge GEC Routines
/**
* Southbridge GEC Controller Public Function
*
*/
/**
* gecInitBeforePciEnum - Config GEC controller before PCI emulation
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID gecInitBeforePciEnum (IN AMDSBCFG* pConfig);
/**
* gecInitAfterPciEnum - Config GEC controller after PCI emulation
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID gecInitAfterPciEnum (IN AMDSBCFG* pConfig);
/**
* gecInitLatePost - Prepare GEC controller to boot to OS.
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID gecInitLatePost (IN AMDSBCFG* pConfig);
// Southbridge USB Routines
/**
* Southbridge USB Controller Public Function
*
*/
/**
* Config USB controller before PCI emulation
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID usbInitBeforePciEnum (IN AMDSBCFG* pConfig);
/**
* Config USB controller after PCI emulation
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID usbInitAfterPciInit (IN AMDSBCFG* pConfig);
/**
* Config USB1 EHCI controller after PCI emulation
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID usb1EhciInitAfterPciInit (IN AMDSBCFG* pConfig);
VOID usb2EhciInitAfterPciInit (IN AMDSBCFG* pConfig);
VOID usb3EhciInitAfterPciInit (IN AMDSBCFG* pConfig);
VOID usb1OhciInitAfterPciInit (IN AMDSBCFG* pConfig);
VOID usb2OhciInitAfterPciInit (IN AMDSBCFG* pConfig);
VOID usb3OhciInitAfterPciInit (IN AMDSBCFG* pConfig);
VOID usb4OhciInitAfterPciInit (IN AMDSBCFG* pConfig);
// Southbridge SMI Service Routines (SMM.C)
/**
* Southbridge SMI Service Routines Public Function
*
*/
/**
* Southbridge SMI service module
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID sbSmmService (IN AMDSBCFG* pConfig);
/**
* softwareSMIservice - Software SMI service
*
* ** Eric
*
* @param[in] VOID Southbridge software SMI service ID.
*
*/
VOID softwareSMIservice (IN VOID);
// Southbridge GPP Controller Routines
/**
* Southbridge GPP Controller Routines Public Function
*
*/
/**
* GPP early programming and link training. On exit all populated EPs should be fully operational.
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID sbPcieGppEarlyInit (IN AMDSBCFG* pConfig);
/**
* sbPcieGppLateInit - Late PCIE initialization for SB800 GPP component
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID sbPcieGppLateInit (IN AMDSBCFG* pConfig);
// Southbridge HD Controller Routines (AZALIA.C)
/**
* Southbridge HD Controller Routines (AZALIA.C) Public Function
*
*/
/**
* Config HD Audio Before PCI emulation
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID azaliaInitBeforePciEnum (IN AMDSBCFG* pConfig);
/**
* Config HD Audio after PCI emulation
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID azaliaInitAfterPciEnum (IN AMDSBCFG* pConfig);
// Southbridge EC Routines
#ifndef NO_EC_SUPPORT
/**
* Southbridge EC Controller Public Function
*
*/
/**
* Config EC controller during power-on
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID ecPowerOnInit (IN AMDSBCFG* pConfig);
/**
* Config EC controller before PCI emulation
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID ecInitBeforePciEnum (IN AMDSBCFG* pConfig);
/**
* Prepare EC controller to boot to OS.
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID ecInitLatePost (IN AMDSBCFG* pConfig);
/**
* validateImcFirmware - Validate IMC Firmware.
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
* @retval TRUE Pass
* @retval FALSE Failed
*/
BOOLEAN validateImcFirmware (IN AMDSBCFG* pConfig);
/**
* validateImcFirmware - Validate IMC Firmware.
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID softwareToggleImcStrapping (IN AMDSBCFG* pConfig);
#endif
#ifndef NO_HWM_SUPPORT
/**
* validateImcFirmware - Validate IMC Firmware.
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID hwmInit (IN AMDSBCFG* pConfig);
#endif

1111
src/vendorcode/amd/cimx/sb800/SBTYPE.h Normal file
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76
src/vendorcode/amd/cimx/sb800/SMM.c Normal file
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/**
* @file
*
* Southbridge SMM service function
*
* Prepare SMM service module for IBV call Southbridge SMI service routine.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: CIMx-SB
* @e sub-project:
* @e \$Revision:$ @e \$Date:$
*
*/
/*
*****************************************************************************
*
* This file is part of the coreboot project.
*
* Copyright (C) 2010 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
* ***************************************************************************
*
*/
#include "SBPLATFORM.h"
//
// Declaration of local functions
//
/**
* Southbridge SMI service module
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID
sbSmmService (
IN AMDSBCFG* pConfig
)
{
AMDSBCFG* pTmp; //lx-dummy for /W4 build
pTmp = pConfig;
}
/**
* softwareSMIservice - Software SMI service
*
* @param[in] VOID Southbridge software SMI service ID.
*
*/
VOID
softwareSMIservice (
IN VOID
)
{
}

64
src/vendorcode/amd/cimx/sb800/SbModInf.c Normal file
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/**
* @file
*
* Function dispatcher.
*
*
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: CIMx-SB
* @e sub-project:
* @e \$Revision:$ @e \$Date:$
*
*/
/*
*****************************************************************************
*
* This file is part of the coreboot project.
*
* Copyright (C) 2010 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
* ***************************************************************************
*
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "SBPLATFORM.h"
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/// module header
VOLATILE AMD_MODULE_HEADER mNbModuleHeader = {
'DOM$', ///< Standard AMD module signature
CIMX_SB_ID, ///< Chipset ID
CIMX_SB_REVISION, ///< CIMx version
AmdSbDispatcher, ///< Pointer to the module entry
NULL ///< Pointer link to next module header
};

421
src/vendorcode/amd/cimx/sb800/USB.c Normal file
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/**
* @file
*
* Config Southbridge USB controller
*
* Init USB features.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: CIMx-SB
* @e sub-project:
* @e \$Revision:$ @e \$Date:$
*
*/
/*
*****************************************************************************
*
* This file is part of the coreboot project.
*
* Copyright (C) 2010 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
* ***************************************************************************
*
*/
#include "SBPLATFORM.h"
//
// Declaration of local functions
//
/**
* EhciInitAfterPciInit - Config USB controller after PCI emulation
*
* @param[in] Value Controller PCI config address (bus# + device# + function#)
* @param[in] pConfig Southbridge configuration structure pointer.
*/
VOID EhciInitAfterPciInit (IN UINT32 Value, IN AMDSBCFG* pConfig);
/**
* OhciInitAfterPciInit - Config USB OHCI controller after PCI emulation
*
* @param[in] Value Controller PCI config address (bus# + device# + function#)
* @param[in] pConfig Southbridge configuration structure pointer.
*/
VOID OhciInitAfterPciInit (IN UINT32 Value, IN AMDSBCFG* pConfig);
/**
* SetEhciP11Wr - FIXME
*
* @param[in] Value Controller PCI config address (bus# + device# + function#)
* @param[in] pConfig Southbridge configuration structure pointer.
*/
UINT32 SetEhciPllWr (IN UINT32 Value, IN AMDSBCFG* pConfig);
/**
* usbInitBeforePciEnum - Config USB controller before PCI emulation
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID
usbInitBeforePciEnum (
IN AMDSBCFG* pConfig
)
{
// Disabled All USB controller
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEF, AccWidthUint8, BIT7, 0);
// Clear PM_IO 0x65[4] UsbResetByPciRstEnable, Set this bit so that usb gets reset whenever there is PCIRST.
// Enable UsbResumeEnable (USB PME) * Default value
// In SB700 USB SleepCtrl set as BIT10+BIT9, but SB800 default is BIT9+BIT8 (6 uframes)
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF0, AccWidthUint16 | S3_SAVE, ~BIT2, BIT2 + BIT7 + BIT8 + BIT9);
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEF, AccWidthUint8, 0, pConfig->USBMODE.UsbModeReg);
}
/**
* usbInitAfterPciInit - Config USB controller after PCI emulation
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID
usbInitAfterPciInit (
IN AMDSBCFG* pConfig
)
{
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGED, AccWidthUint8, ~BIT1, BIT1);
usb1EhciInitAfterPciInit (pConfig);
usb2EhciInitAfterPciInit (pConfig);
usb3EhciInitAfterPciInit (pConfig);
usb1OhciInitAfterPciInit (pConfig);
usb2OhciInitAfterPciInit (pConfig);
usb3OhciInitAfterPciInit (pConfig);
usb4OhciInitAfterPciInit (pConfig);
if ( pConfig->UsbPhyPowerDown ) {
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF0, AccWidthUint8, ~BIT0, BIT0);
} else
{
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF0, AccWidthUint8, ~BIT0, 0);
}
}
/**
* usb1EhciInitAfterPciInit - Config USB1 EHCI controller after PCI emulation
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID
usb1EhciInitAfterPciInit (
IN AMDSBCFG* pConfig
)
{
UINT32 ddDeviceId;
ddDeviceId = (USB1_EHCI_BUS_DEV_FUN << 16);
EhciInitAfterPciInit (ddDeviceId, pConfig);
}
/**
* usb2EhciInitAfterPciInit - Config USB2 EHCI controller after PCI emulation
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID
usb2EhciInitAfterPciInit (
IN AMDSBCFG* pConfig
)
{
UINT32 ddDeviceId;
ddDeviceId = (USB2_EHCI_BUS_DEV_FUN << 16);
EhciInitAfterPciInit (ddDeviceId, pConfig);
}
/**
* usb3EhciInitAfterPciInit - Config USB3 EHCI controller after PCI emulation
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID
usb3EhciInitAfterPciInit (
IN AMDSBCFG* pConfig
)
{
UINT32 ddDeviceId;
ddDeviceId = (USB3_EHCI_BUS_DEV_FUN << 16);
EhciInitAfterPciInit (ddDeviceId, pConfig);
}
VOID
EhciInitAfterPciInit (
IN UINT32 Value,
IN AMDSBCFG* pConfig
)
{
UINT32 ddBarAddress;
UINT32 ddVar;
//Get BAR address
ReadPCI ((UINT32) Value + SB_EHCI_REG10, AccWidthUint32, &ddBarAddress);
if ( (ddBarAddress != - 1) && (ddBarAddress != 0) ) {
//Enable Memory access
RWPCI ((UINT32) Value + SB_EHCI_REG04, AccWidthUint8, 0, BIT1);
if (pConfig->BuildParameters.EhciSsid != NULL ) {
RWPCI ((UINT32) Value + SB_EHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.EhciSsid);
}
//USB Common PHY CAL & Control Register setting
ddVar = 0x00020F00;
WriteMEM (ddBarAddress + SB_EHCI_BAR_REGC0, AccWidthUint32, &ddVar);
// RPR IN AND OUT DATA PACKET FIFO THRESHOLD
// EHCI BAR 0xA4 //IN threshold bits[7:0]=0x40 //OUT threshold bits[23:16]=0x40
RWMEM (ddBarAddress + SB_EHCI_BAR_REGA4, AccWidthUint32, 0xFF00FF00, 0x00400040);
// RPR EHCI Dynamic Clock Gating Feature
RWMEM (ddBarAddress + SB_EHCI_BAR_REGBC, AccWidthUint32, ~BIT12, 0);
// RPR Enable adding extra flops to PHY rsync path
// Step 1:
// EHCI_BAR 0xB4 [6] = 1
// EHCI_BAR 0xB4 [7] = 0
// EHCI_BAR 0xB4 [12] = 0 ("VLoad")
// All other bit field untouched
// Step 2:
// EHCI_BAR 0xB4[12] = 1
RWMEM (ddBarAddress + SB_EHCI_BAR_REGB4, AccWidthUint32, ~(BIT6 + BIT7 + BIT12), 0x00);
RWMEM (ddBarAddress + SB_EHCI_BAR_REGB4, AccWidthUint32, ~BIT12, BIT12);
//Set EHCI_pci_configx50[6]='1' to disable EHCI MSI support
//RPR recommended setting "EHCI Async Park Mode"
//Set EHCI_pci_configx50[23]='0' to enable "EHCI Async Park Mode support"
//RPR Enabling EHCI Async Stop Enhancement
//Set EHCI_pci_configx50[29]='1' to disableEnabling EHCI Async Stop Enhancement
RWPCI ((UINT32) Value + SB_EHCI_REG50, AccWidthUint32 | S3_SAVE, ~(BIT23), BIT29 + BIT23 + BIT8 + BIT6);
// RPR recommended setting "EHCI Advance PHY Power Savings"
// Set EHCI_pci_configx50[31]='1'
// Fix for EHCI controller driver yellow sign issue under device manager
// when used in conjunction with HSET tool driver. EHCI PCI config 0x50[20]=1
RWPCI ((UINT32) Value + SB_EHCI_REG50 + 2, AccWidthUint16 | S3_SAVE, (UINT16)0xFFFF, BIT15);
// RPR USB Delay A-Link Express L1 State
// RPR PING Response Fix Enable EHCI_PCI_Config x54[1] = 1
// RPR Empty-list Detection Fix Enable EHCI_PCI_Config x54[3] = 1
RWPCI ((UINT32) Value + SB_EHCI_REG54, AccWidthUint32 | S3_SAVE, ~BIT0, BIT0);
if ( pConfig->BuildParameters.UsbMsi) {
RWPCI ((UINT32) Value + SB_EHCI_REG50, AccWidthUint32 | S3_SAVE, ~BIT6, 0x00);
}
}
}
/**
* usb1OhciInitAfterPciInit - Config USB1 OHCI controller after PCI emulation
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID
usb1OhciInitAfterPciInit (
IN AMDSBCFG* pConfig
)
{
UINT32 ddDeviceId;
ddDeviceId = (USB1_OHCI_BUS_DEV_FUN << 16);
OhciInitAfterPciInit (ddDeviceId, pConfig);
}
/**
* usb2OhciInitAfterPciInit - Config USB2 OHCI controller after PCI emulation
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID
usb2OhciInitAfterPciInit (
IN AMDSBCFG* pConfig
)
{
UINT32 ddDeviceId;
ddDeviceId = (USB2_OHCI_BUS_DEV_FUN << 16);
OhciInitAfterPciInit (ddDeviceId, pConfig);
}
/**
* usb3OhciInitAfterPciInit - Config USB3 OHCI controller after PCI emulation
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID
usb3OhciInitAfterPciInit (
IN AMDSBCFG* pConfig
)
{
UINT32 ddDeviceId;
ddDeviceId = (USB3_OHCI_BUS_DEV_FUN << 16);
OhciInitAfterPciInit (ddDeviceId, pConfig);
}
/**
* usb4OhciInitAfterPciInit - Config USB4 OHCI controller after PCI emulation
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID
usb4OhciInitAfterPciInit (
IN AMDSBCFG* pConfig
)
{
UINT32 ddDeviceId;
ddDeviceId = (USB4_OHCI_BUS_DEV_FUN << 16);
OhciInitAfterPciInit (ddDeviceId, pConfig);
if (pConfig->BuildParameters.Ohci4Ssid != NULL ) {
RWPCI ((USB4_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.Ohci4Ssid);
}
}
VOID
OhciInitAfterPciInit (
IN UINT32 Value,
IN AMDSBCFG* pConfig
)
{
// Disable the MSI capability of USB host controllers
RWPCI ((UINT32) Value + SB_OHCI_REG40 + 1, AccWidthUint8 | S3_SAVE, 0xFF, BIT0);
RWPCI ((UINT32) Value + SB_OHCI_REG50, AccWidthUint8 | S3_SAVE, ~(BIT5 + BIT12), 0x00);
// RPR USB SMI Handshake
RWPCI ((UINT32) Value + SB_OHCI_REG50 + 1, AccWidthUint8 | S3_SAVE, ~BIT4, 0x00);
// SB02186
RWPCI ((UINT32) Value + SB_OHCI_REG50 + 1, AccWidthUint8 | S3_SAVE, 0xFC, 0x00);
if (Value != (USB4_OHCI_BUS_DEV_FUN << 16)) {
if ( pConfig->BuildParameters.OhciSsid != NULL ) {
RWPCI ((UINT32) Value + SB_OHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.OhciSsid);
}
}
//RPR recommended setting to, enable fix to cover the corner case S3 wake up issue from some USB 1.1 devices
//OHCI 0_PCI_Config 0x50[30] = 1
RWPCI ((UINT32) Value + SB_OHCI_REG50 + 3, AccWidthUint8 | S3_SAVE, ~BIT6, BIT6);
if ( pConfig->BuildParameters.UsbMsi) {
RWPCI ((UINT32) Value + SB_OHCI_REG40 + 1, AccWidthUint8 | S3_SAVE, ~BIT0, 0x00);
RWPCI ((UINT32) Value + SB_OHCI_REG50, AccWidthUint8 | S3_SAVE, ~BIT5, BIT5);
}
}
UINT32
SetEhciPllWr (
IN UINT32 Value,
IN AMDSBCFG* pConfig
)
{
UINT32 ddRetureValue;
UINT32 ddBarAddress;
UINT16 dwVar;
UINT16 dwData;
UINT8 portSC;
ddRetureValue = 0;
dwData = 0;
// Memory, and etc.
//_asm { jmp $};
RWPCI ((UINT32) Value + 0xC4, AccWidthUint8, 0xF0, 0x00);
RWPCI ((UINT32) Value + 0x04, AccWidthUint8, 0xFF, 0x02);
// Get Bar address
ReadPCI ((UINT32) Value + 0x10, AccWidthUint32, &ddBarAddress);
for (portSC = 0x64; portSC < 0x75; portSC += 0x04 ) {
// Get OHCI command registers
ReadMEM (ddBarAddress + portSC, AccWidthUint16, &dwVar);
if ( dwVar & BIT6 ) {
ddRetureValue = ddBarAddress + portSC;
RWMEM (ddBarAddress + portSC, AccWidthUint16, ~BIT6, 0);
for (;;) {
SbStall (5);
ReadMEM (ddBarAddress + portSC, AccWidthUint16, &dwData);
if (dwData == 0x1005) break;
}
dwData = 0;
}
}
return ddRetureValue;
}
VOID
usbSetPllDuringS3 (
IN AMDSBCFG* pConfig
)
{
UINT32 resumeEhciPortTmp;
UINT32 resumeEhciPort;
resumeEhciPortTmp = 0;
resumeEhciPort = 0;
// UINT32 ddDeviceId;
//if Force Port Resume == 1
// {
// clear Force Port Resume;
// while (!(PORTSC == 0x1005)){wait 5 us; read PORTSC;}
// }
if (pConfig->USBMODE.UsbModeReg & BIT1) {
resumeEhciPortTmp = SetEhciPllWr (USB1_EHCI_BUS_DEV_FUN << 16, pConfig);
if (resumeEhciPortTmp > 0) resumeEhciPort = resumeEhciPortTmp;
}
if (pConfig->USBMODE.UsbModeReg & BIT3) {
resumeEhciPortTmp = SetEhciPllWr (USB2_EHCI_BUS_DEV_FUN << 16, pConfig);
if (resumeEhciPortTmp > 0) resumeEhciPort = resumeEhciPortTmp;
}
if (pConfig->USBMODE.UsbModeReg & BIT5) {
resumeEhciPortTmp = SetEhciPllWr (USB3_EHCI_BUS_DEV_FUN << 16, pConfig);
if (resumeEhciPortTmp > 0) resumeEhciPort = resumeEhciPortTmp;
}
RWPCI ((UINT32) (USB1_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG50, AccWidthUint32, ~BIT29, 0);
RWPCI ((UINT32) (USB2_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG50, AccWidthUint32, ~BIT29, 0);
RWPCI ((UINT32) (USB3_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG50, AccWidthUint32, ~BIT29, 0);
RWPCI ((UINT32) (USB4_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG50, AccWidthUint32, ~BIT29, 0);
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF3, AccWidthUint8, 0, 0x20);
SbStall (10);
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF3, AccWidthUint8, 0, 0x00);
RWPCI ((UINT32) (USB1_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG50, AccWidthUint32, ~BIT29, BIT29);
RWPCI ((UINT32) (USB2_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG50, AccWidthUint32, ~BIT29, BIT29);
RWPCI ((UINT32) (USB3_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG50, AccWidthUint32, ~BIT29, BIT29);
RWPCI ((UINT32) (USB4_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG50, AccWidthUint32, ~BIT29, BIT29);
if (resumeEhciPort > 0) {
RWMEM (resumeEhciPort, AccWidthUint8, ~BIT7, BIT7);
SbStall (4000);
RWMEM (resumeEhciPort, AccWidthUint8, ~BIT6, BIT6);
}
RWPCI ((UINT32) (USB1_EHCI_BUS_DEV_FUN << 16) + 0xC4, AccWidthUint8, 0xF0, 0x03);
RWPCI ((UINT32) (USB2_EHCI_BUS_DEV_FUN << 16) + 0xC4, AccWidthUint8, 0xF0, 0x03);
RWPCI ((UINT32) (USB3_EHCI_BUS_DEV_FUN << 16) + 0xC4, AccWidthUint8, 0xF0, 0x03);
}