From 79ab7d7780bfb0a23748afdd5b4832e23544b4df Mon Sep 17 00:00:00 2001
From: Raul E Rangel <rrangel@chromium.org>
Date: Mon, 13 Jul 2020 16:33:07 -0600
Subject: [PATCH] soc/amd/picasso/acpi,mb/{zork,mandolin}: Stop clearing
 PciExpWakeStatus

The kernel already clears this: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/master:src/third_party/kernel/v5.4/drivers/acpi/acpica/hwregs.c;l=390
No reason to have the firmware do it as well.

BUG=b:153001807, b:154756391
TEST=Build Trembyle, boot, suspend, and resume and didn't see any ACPI
errors.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ia5c79fb95dc885eaef8abc4257b6ba18c1ef1b66
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43428
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
---
 src/mainboard/amd/mandolin/acpi/sleep.asl      |  2 --
 .../baseboard/include/baseboard/acpi/sleep.asl |  2 --
 src/soc/amd/picasso/acpi/pcie.asl              | 18 ------------------
 3 files changed, 22 deletions(-)

diff --git a/src/mainboard/amd/mandolin/acpi/sleep.asl b/src/mainboard/amd/mandolin/acpi/sleep.asl
index 6fdb30b5d4..526754e429 100644
--- a/src/mainboard/amd/mandolin/acpi/sleep.asl
+++ b/src/mainboard/amd/mandolin/acpi/sleep.asl
@@ -21,8 +21,6 @@ Method(_PTS, 1) {
 	/* DBGO("From S0 to S") */
 	/* DBGO(Arg0) */
 	/* DBGO("\n") */
-
-	Store(0, PEWD)
 } /* End Method(\_PTS) */
 
 /*
diff --git a/src/mainboard/google/zork/variants/baseboard/include/baseboard/acpi/sleep.asl b/src/mainboard/google/zork/variants/baseboard/include/baseboard/acpi/sleep.asl
index 267be30095..4a62ecf2db 100644
--- a/src/mainboard/google/zork/variants/baseboard/include/baseboard/acpi/sleep.asl
+++ b/src/mainboard/google/zork/variants/baseboard/include/baseboard/acpi/sleep.asl
@@ -21,8 +21,6 @@ Method(_PTS, 1) {
 	/* DBGO("From S0 to S") */
 	/* DBGO(Arg0) */
 	/* DBGO("\n") */
-
-	Store(0, PEWD)
 } /* End Method(\_PTS) */
 
 /*
diff --git a/src/soc/amd/picasso/acpi/pcie.asl b/src/soc/amd/picasso/acpi/pcie.asl
index cb4be7fcaf..601de5247e 100644
--- a/src/soc/amd/picasso/acpi/pcie.asl
+++ b/src/soc/amd/picasso/acpi/pcie.asl
@@ -63,21 +63,3 @@
 		IUA2, 0x00000008,	/* Index 0xF8: UART2 */
 		IUA3, 0x00000008,	/* Index 0xF9: UART3 */
 	}
-
-	/* Power Management I/O registers, TODO:PMIO is quite different in SB800. */
-	OperationRegion(PIOR, SystemIO, 0x00000Cd6, 0x00000002)
-		Field(PIOR, ByteAcc, NoLock, Preserve) {
-		PIOI, 0x00000008,
-		PIOD, 0x00000008,
-	}
-
-	IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) {
-		Offset(0x60),		/* AcpiPm1EvgBlk */
-		P1EB, 16,
-	}
-	OperationRegion (P1E0, SystemIO, P1EB, 0x04)
-		Field (P1E0, ByteAcc, Nolock, Preserve) {
-		Offset(0x02),
-		, 14,
-		PEWD, 1,
-	}