Move some board specific functions to sb800.h.
Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Zheng Bao <zheng.bao@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6279 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Zheng Bao
Zheng Bao
parent
8210e8972c
commit
79c04d559a
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@ -61,7 +61,7 @@ static void sb800_acpi_init(void) {
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pmio_write(0x6C, ACPI_PMA_CNT_BLK & 0xFF);
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pmio_write(0x6D, ACPI_PMA_CNT_BLK >> 8);
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pm_iowrite(0x74, 1<<0 | 1<<1 | 1<<4 | 1<<2); /* AcpiDecodeEnable, When set, SB uses
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pmio_write(0x74, 1<<0 | 1<<1 | 1<<4 | 1<<2); /* AcpiDecodeEnable, When set, SB uses
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* the contents of the PM registers at
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* index 60-6B to decode ACPI I/O address.
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* AcpiSmiEn & SmiCmdEn*/
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@ -95,8 +95,7 @@ static u8 get_sb800_revision(void)
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return rev;
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}
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#if 0
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static void sb800_clk_output_48Mhz(void)
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void sb800_clk_output_48Mhz(void)
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{
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/* AcpiMMioDecodeEn */
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u8 reg8;
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@ -108,7 +107,6 @@ static void sb800_clk_output_48Mhz(void)
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*(volatile u32 *)(0xFED80000+0xE00+0x40) &= ~((1 << 0) | (1 << 2)); /* 48Mhz */
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*(volatile u32 *)(0xFED80000+0xE00+0x40) |= 1 << 1; /* 48Mhz */
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}
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#endif
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/***************************************
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* Legacy devices are mapped to LPC space.
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* Serial port 0
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@ -234,8 +232,7 @@ void soft_reset(void)
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outb(0x06, 0x0cf9);
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}
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#if 0
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static void sb800_pci_port80(void)
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void sb800_pci_port80(void)
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{
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u8 byte;
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device_t dev;
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@ -279,7 +276,7 @@ static void sb800_pci_port80(void)
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byte &= ~(1 << 5); /* disable lpc port 80 */
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pci_write_config8(dev, 0x4A, byte);
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}
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#endif
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#define BIT0 (1 << 0)
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#define BIT1 (1 << 1)
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#define BIT2 (1 << 2)
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@ -296,54 +293,52 @@ struct pm_entry {
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};
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struct pm_entry const pm_table[] =
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{
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{0x5D, 0x00, BIT0},
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{0xD2, 0xCF, BIT4 + BIT5},
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{0x12, 0x00, BIT0},
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{0x28, 0xFF, BIT0},
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{0x44 + 3, 0x7F, BIT7},
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{0x48, 0xFF, BIT0},
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{0x00, 0xFF, 0x0E},
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{0x00 + 2, 0xFF, 0x40},
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{0x00 + 3, 0xFF, 0x08},
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{0x34, 0xEF, BIT0 + BIT1},
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{0xEC, 0xFD, BIT1},
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{0x5B, 0xF9, BIT1 + BIT2},
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{0x08, 0xFE, BIT2 + BIT4},
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{0x08 + 1, 0xFF, BIT0},
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{0x54, 0x00, BIT4 + BIT7},
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{0x04 + 3, 0xFD, BIT1},
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{0x74, 0xF6, BIT0 + BIT3},
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{0xF0, ~BIT2, 0x00},
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{0xF8, 0x00, 0x6C},
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{0xF8 + 1, 0x00, 0x27},
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{0xF8 + 2, 0x00, 0x00},
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{0xC4, 0xFE, 0x14},
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{0xC0 + 2, 0xBF, 0x40},
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{0xBE, 0xDD, BIT5},
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// HPET workaround
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{0x54 + 3, 0xFC, BIT0 + BIT1},
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{0x54 + 2, 0x7F, BIT7},
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{0x54 + 2, 0x7F, 0x00},
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{0xC4, ~(BIT2 + BIT4), BIT2 + BIT4},
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{0xC0, 0, 0xF9},
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{0xC0 + 1, 0x04, 0x03},
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{0xC2, 0x20, 0x58},
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{0xC2 + 1, 0, 0x40},
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{0xC2, ~(BIT4), BIT4},
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{0x74, 0x00, BIT0 + BIT1 + BIT2 + BIT4},
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{0xDE + 1, ~(BIT0 + BIT1), BIT0 + BIT1},
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{0xDE, ~BIT4, BIT4},
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{0xBA, ~BIT3, BIT3},
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{0xBA + 1, ~BIT6, BIT6},
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{0xBC, ~BIT1, BIT1},
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{0xED, ~(BIT0 + BIT1), 0},
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{0xDC, 0x7C, BIT0},
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{0x5D, 0x00, BIT0},
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{0xD2, 0xCF, BIT4 + BIT5},
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{0x12, 0x00, BIT0},
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{0x28, 0xFF, BIT0},
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{0x44 + 3, 0x7F, BIT7},
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{0x48, 0xFF, BIT0},
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{0x00, 0xFF, 0x0E},
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{0x00 + 2, 0xFF, 0x40},
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{0x00 + 3, 0xFF, 0x08},
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{0x34, 0xEF, BIT0 + BIT1},
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{0xEC, 0xFD, BIT1},
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{0x5B, 0xF9, BIT1 + BIT2},
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{0x08, 0xFE, BIT2 + BIT4},
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{0x08 + 1, 0xFF, BIT0},
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{0x54, 0x00, BIT4 + BIT7},
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{0x04 + 3, 0xFD, BIT1},
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{0x74, 0xF6, BIT0 + BIT3},
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{0xF0, ~BIT2, 0x00},
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{0xF8, 0x00, 0x6C},
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{0xF8 + 1, 0x00, 0x27},
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{0xF8 + 2, 0x00, 0x00},
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{0xC4, 0xFE, 0x14},
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{0xC0 + 2, 0xBF, 0x40},
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{0xBE, 0xDD, BIT5},
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// HPET workaround
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{0x54 + 3, 0xFC, BIT0 + BIT1},
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{0x54 + 2, 0x7F, BIT7},
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{0x54 + 2, 0x7F, 0x00},
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{0xC4, ~(BIT2 + BIT4), BIT2 + BIT4},
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{0xC0, 0, 0xF9},
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{0xC0 + 1, 0x04, 0x03},
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{0xC2, 0x20, 0x58},
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{0xC2 + 1, 0, 0x40},
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{0xC2, ~(BIT4), BIT4},
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{0x74, 0x00, BIT0 + BIT1 + BIT2 + BIT4},
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{0xDE + 1, ~(BIT0 + BIT1), BIT0 + BIT1},
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{0xDE, ~BIT4, BIT4},
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{0xBA, ~BIT3, BIT3},
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{0xBA + 1, ~BIT6, BIT6},
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{0xBC, ~BIT1, BIT1},
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{0xED, ~(BIT0 + BIT1), 0},
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{0xDC, 0x7C, BIT0},
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// {0xFF, 0xFF, 0xFF},
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};
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static void sb800_lpc_port80(void)
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void sb800_lpc_port80(void)
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{
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u8 byte;
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device_t dev;
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@ -47,12 +47,13 @@ extern void set_sm_enable_bits(device_t sm_dev, u32 reg_pos, u32 mask, u32 val);
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#define REV_SB800_A11 0x11
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#define REV_SB800_A12 0x12
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/* This shouldn't be called before set_sb800_revision() is called.
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* Once set_sb800_revision() is called, we use get_sb800_revision(),
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* the simpler one, to get the sb800 revision ID.
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* The id is 0x39 if A11, 0x3A if A12, 0x3C if A14, 0x3D if A15.
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* The differentiate is 0x28, isn't it? */
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//#define get_sb800_revision(sm_dev) (pci_read_config8((sm_dev), 0x08) - 0x28)
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#ifdef __PRE_RAM__
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void sb800_lpc_port80(void);
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void sb800_pci_port80(void);
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void sb800_clk_output_48Mhz(void);
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#else
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/* void sb800_setup_sata_phys(struct device *dev); */
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#endif
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void sb800_enable(device_t dev);
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void sb800_enable_usbdebug(unsigned int port);
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