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Revert "soc/amd/common/block/acpimmio: Update acpimmio for psp_verstage" 

This reverts commit 4883252912.

Almost everything in <amdblocks/acpimmio_map.h> is invalid for PSP as
it does not have the same view of memory space.

The prototypes xx_set/get_bar() are only valid for PSP as x86 cores
will use the constant mapping defined in <amdblocks/acpimmio_map.h>

The selected MMIO base address model depends of the architecture the
stage is built for and, to current knowledge, nothing else. So
the guards should have been with ENV_X86 vs ENV_ARM and not about
CONFIG(VERSTAGE_BEFORE_BOOTBLOCK).

For the ENV_ARM stage builds, <arch/io.h> file referenced in the
previously added mmio_util_psp.c file has not been added to the tree.
So there was some out-of-order submitting, which did not get caught
as the build-testing of mixed-arch stages has not been incorporated
into the tree yet.

The previously added file mmio_util_psp.c is also 90% redundant with
mmio_util.c.

Change-Id: I1d632f52745bc6cd3c3dbddb1ea5ff9ba962c2e8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42486
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kyösti Mälkki 2020-06-17 23:55:41 +03:00 committed by Patrick Georgi
parent e8afb0ee92
commit 79d41263d9
3 changed files with 2 additions and 202 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
src/soc/amd/common/block/acpimmio/Makefile.inc
View File

@ -1,17 +1,13 @@
bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += mmio_util.c
verstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += mmio_util.c
romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += mmio_util.c
postcar-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += mmio_util.c
ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += mmio_util.c
smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += mmio_util.c
bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += biosram.c
verstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += biosram.c
romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += biosram.c
postcar-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += biosram.c
ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += biosram.c
smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += biosram.c
ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO),y)
verstage-$(CONFIG_ARCH_VERSTAGE_X86_32) += biosram.c
verstage-$(CONFIG_ARCH_VERSTAGE_X86_32) += mmio_util.c
verstage-$(CONFIG_ARCH_VERSTAGE_ARM) += mmio_util_psp.c
endif

163
src/soc/amd/common/block/acpimmio/mmio_util_psp.c
View File

@ -1,163 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <stdint.h>
#include <arch/io.h>
#include <device/mmio.h>
#include <amdblocks/acpimmio.h>
static uintptr_t iomux_bar;
void iomux_set_bar(void *bar)
{
iomux_bar = (uintptr_t)bar;
}
u8 iomux_read8(u8 reg)
{
return read8((void *)(iomux_bar + reg));
}
u16 iomux_read16(u8 reg)
{
return read16((void *)(iomux_bar + reg));
}
u32 iomux_read32(u8 reg)
{
return read32((void *)(iomux_bar + reg));
}
void iomux_write8(u8 reg, u8 value)
{
write8((void *)(iomux_bar + reg), value);
}
void iomux_write16(u8 reg, u16 value)
{
write16((void *)(iomux_bar + reg), value);
}
void iomux_write32(u8 reg, u32 value)
{
write32((void *)(iomux_bar + reg), value);
}
static uintptr_t misc_bar;
void misc_set_bar(void *bar)
{
misc_bar = (uintptr_t)bar;
}
u8 misc_read8(u8 reg)
{
return read8((void *)(misc_bar + reg));
}
u16 misc_read16(u8 reg)
{
return read16((void *)(misc_bar + reg));
}
u32 misc_read32(u8 reg)
{
return read32((void *)(misc_bar + reg));
}
void misc_write8(u8 reg, u8 value)
{
write8((void *)(misc_bar + reg), value);
}
void misc_write16(u8 reg, u16 value)
{
write16((void *)(misc_bar + reg), value);
}
void misc_write32(u8 reg, u32 value)
{
write32((void *)(misc_bar + reg), value);
}
static uintptr_t gpio_bar;
void gpio_set_bar(void *bar)
{
gpio_bar = (uintptr_t)bar;
}
void *gpio_get_bar(void)
{
return (void *)gpio_bar;
}
static uintptr_t aoac_bar;
void aoac_set_bar(void *bar)
{
aoac_bar = (uintptr_t)bar;
}
u8 aoac_read8(u8 reg)
{
return read8((void *)(aoac_bar + reg));
}
void aoac_write8(u8 reg, u8 value)
{
write8((void *)(aoac_bar + reg), value);
}
static uintptr_t io_bar;
void io_set_bar(void *bar)
{
io_bar = (uintptr_t)bar;
}
u8 io_read8(u16 reg)
{
return read8((void *)(io_bar + reg));
}
void io_write8(u16 reg, u8 value)
{
write8((void *)(io_bar + reg), value);
}
/* PM registers are accessed a byte at a time via CD6/CD7 */
uint8_t pm_io_read8(uint8_t reg)
{
outb(reg, PM_INDEX);
return inb(PM_DATA);
}
uint16_t pm_io_read16(uint8_t reg)
{
return (pm_io_read8(reg + sizeof(uint8_t)) << 8) | pm_io_read8(reg);
}
uint32_t pm_io_read32(uint8_t reg)
{
return (pm_io_read16(reg + sizeof(uint16_t)) << 16) | pm_io_read16(reg);
}
void pm_io_write8(uint8_t reg, uint8_t value)
{
outb(reg, PM_INDEX);
outb(value, PM_DATA);
}
void pm_io_write16(uint8_t reg, uint16_t value)
{
pm_io_write8(reg, value & 0xff);
value >>= 8;
pm_io_write8(reg + sizeof(uint8_t), value & 0xff);
}
void pm_io_write32(uint8_t reg, uint32_t value)
{
pm_io_write16(reg, value & 0xffff);
value >>= 16;
pm_io_write16(reg + sizeof(uint16_t), value & 0xffff);
}

33
src/soc/amd/common/block/include/amdblocks/acpimmio.h
View File

@ -100,38 +100,6 @@ void pm_io_write8(uint8_t reg, uint8_t value);
void pm_io_write16(uint8_t reg, uint16_t value);
void pm_io_write32(uint8_t reg, uint32_t value);
void iomux_set_bar(void *bar);
void *iomux_get_bar(void);
void misc_set_bar(void *bar);
void *misc_get_bar(void);
void gpio_set_bar(void *bar);
void *gpio_get_bar(void);
void aoac_set_bar(void *bar);
void *aoac_get_bar(void);
void io_set_bar(void *bar);
u8 io_read8(u16 reg);
void io_write8(u16 reg, u8 value);
#if (CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK) && ENV_SEPARATE_VERSTAGE)
u8 iomux_read8(u8 reg);
u16 iomux_read16(u8 reg);
u32 iomux_read32(u8 reg);
void iomux_write8(u8 reg, u8 value);
void iomux_write16(u8 reg, u16 value);
void iomux_write32(u8 reg, u32 value);
u8 misc_read8(u8 reg);
u16 misc_read16(u8 reg);
u32 misc_read32(u8 reg);
void misc_write8(u8 reg, u8 value);
void misc_write16(u8 reg, u16 value);
void misc_write32(u8 reg, u32 value);
u8 aoac_read8(u8 reg);
void aoac_write8(u8 reg, u8 value);
#else
static inline uint8_t sm_pci_read8(uint8_t reg)
{
return read8((void *)(ACPIMMIO_SM_PCI_BASE + reg));
@ -547,5 +515,4 @@ static inline void aoac_write8(uint8_t reg, uint8_t value)
write8((void *)(ACPIMMIO_AOAC_BASE + reg), value);
}
#endif /* (CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK) && ENV_SEPARATE_VERSTAGE) */
#endif /* __AMDBLOCKS_ACPIMMIO_H__ */