GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

nb/intel/haswell/acpi: Merge `haswell.asl` into `hostbridge.asl` 

Tested with BUILD_TIMELESS=1, Google Wolf remains identical.

Change-Id: I710581156937b042ba4cf5948c65d0795ad37bbf
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46789
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons 2020-10-25 23:44:30 +01:00 committed by Michael Niewöhner
parent e339f9505b
commit 79e3a1f8a5
9 changed files with 42 additions and 42 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/mainboard/asrock/b85m_pro4/dsdt.asl
View File

@ -20,7 +20,7 @@ DefinitionBlock(
Device (\_SB.PCI0)
{
#include <northbridge/intel/haswell/acpi/haswell.asl>
#include <northbridge/intel/haswell/acpi/hostbridge.asl>
#include <southbridge/intel/lynxpoint/acpi/pch.asl>
#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
}

2
src/mainboard/asrock/h81m-hds/dsdt.asl
View File

@ -20,7 +20,7 @@ DefinitionBlock(
{
Device (PCI0)
{
#include <northbridge/intel/haswell/acpi/haswell.asl>
#include <northbridge/intel/haswell/acpi/hostbridge.asl>
#include <southbridge/intel/lynxpoint/acpi/pch.asl>
#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
}

2
src/mainboard/google/beltino/dsdt.asl
View File

@ -24,7 +24,7 @@ DefinitionBlock(
Scope (\_SB) {
Device (PCI0)
{
#include <northbridge/intel/haswell/acpi/haswell.asl>
#include <northbridge/intel/haswell/acpi/hostbridge.asl>
#include <southbridge/intel/lynxpoint/acpi/pch.asl>
}
}

2
src/mainboard/google/slippy/dsdt.asl
View File

@ -24,7 +24,7 @@ DefinitionBlock(
Scope (\_SB) {
Device (PCI0)
{
#include <northbridge/intel/haswell/acpi/haswell.asl>
#include <northbridge/intel/haswell/acpi/hostbridge.asl>
#include <southbridge/intel/lynxpoint/acpi/pch.asl>
#include <drivers/intel/gma/acpi/default_brightness_levels.asl>

2
src/mainboard/intel/baskingridge/dsdt.asl
View File

@ -24,7 +24,7 @@ DefinitionBlock(
Scope (\_SB) {
Device (PCI0)
{
#include <northbridge/intel/haswell/acpi/haswell.asl>
#include <northbridge/intel/haswell/acpi/hostbridge.asl>
#include <southbridge/intel/lynxpoint/acpi/pch.asl>
#include <drivers/intel/gma/acpi/default_brightness_levels.asl>

2
src/mainboard/lenovo/t440p/dsdt.asl
View File

@ -24,7 +24,7 @@ DefinitionBlock(
Device (\_SB.PCI0)
{
#include <northbridge/intel/haswell/acpi/haswell.asl>
#include <northbridge/intel/haswell/acpi/hostbridge.asl>
#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
#include <southbridge/intel/lynxpoint/acpi/pch.asl>
}

2
src/mainboard/supermicro/x10slm-f/dsdt.asl
View File

@ -19,7 +19,7 @@ DefinitionBlock(
Device (\_SB.PCI0)
{
#include <northbridge/intel/haswell/acpi/haswell.asl>
#include <northbridge/intel/haswell/acpi/hostbridge.asl>
#include <southbridge/intel/lynxpoint/acpi/pch.asl>
#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
}

35
src/northbridge/intel/haswell/acpi/haswell.asl
View File

@ -1,35 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include "../haswell.h"
#include "hostbridge.asl"
#include "peg.asl"
#include <southbridge/intel/common/rcba.h>
/* PCI Device Resource Consumption */
Device (PDRC)
{
Name (_HID, EISAID ("PNP0C02"))
Name (_UID, 1)
Name (PDRS, ResourceTemplate () {
Memory32Fixed (ReadWrite, DEFAULT_RCBA, 0x00004000)
Memory32Fixed (ReadWrite, DEFAULT_MCHBAR, 0x00008000)
Memory32Fixed (ReadWrite, DEFAULT_DMIBAR, 0x00001000)
Memory32Fixed (ReadWrite, DEFAULT_EPBAR, 0x00001000)
Memory32Fixed (ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, 0x04000000)
Memory32Fixed (ReadWrite, 0xfed20000, 0x00020000) // Misc ICH
Memory32Fixed (ReadWrite, 0xfed40000, 0x00005000) // Misc ICH
Memory32Fixed (ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH
#if CONFIG(CHROMEOS_RAMOOPS)
Memory32Fixed (ReadWrite, CONFIG_CHROMEOS_RAMOOPS_RAM_START,
CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE)
#endif
})
// Current Resource Settings
Method (_CRS, 0, Serialized)
{
Return (PDRS)
}
}

35
src/northbridge/intel/haswell/acpi/hostbridge.asl
View File

@ -1,5 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include "../haswell.h"
#include <southbridge/intel/common/rcba.h>
Name (_HID, EISAID ("PNP0A08")) // PCIe
Name (_CID, EISAID ("PNP0A03")) // PCI
@ -167,3 +170,35 @@ Method (_CRS, 0, Serialized)
/* Configurable TDP */
#include "ctdp.asl"
/* PCI Express Graphics */
#include "peg.asl"
/* PCI Device Resource Consumption */
Device (PDRC)
{
Name (_HID, EISAID ("PNP0C02"))
Name (_UID, 1)
Name (PDRS, ResourceTemplate () {
Memory32Fixed (ReadWrite, DEFAULT_RCBA, 0x00004000)
Memory32Fixed (ReadWrite, DEFAULT_MCHBAR, 0x00008000)
Memory32Fixed (ReadWrite, DEFAULT_DMIBAR, 0x00001000)
Memory32Fixed (ReadWrite, DEFAULT_EPBAR, 0x00001000)
Memory32Fixed (ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, 0x04000000)
Memory32Fixed (ReadWrite, 0xfed20000, 0x00020000) // Misc ICH
Memory32Fixed (ReadWrite, 0xfed40000, 0x00005000) // Misc ICH
Memory32Fixed (ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH
#if CONFIG(CHROMEOS_RAMOOPS)
Memory32Fixed (ReadWrite, CONFIG_CHROMEOS_RAMOOPS_RAM_START,
CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE)
#endif
})
// Current Resource Settings
Method (_CRS, 0, Serialized)
{
Return (PDRS)
}
}