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soc/intel/alderlake/include/soc/iomap.h: Add ADL PCH-S reserved spaces 

PCH-S maps certain MMIO BARs differently than low power PCHs. The
reserved ranges taken from Intel DOC #630603.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ifefedc629def207ecd6f7be792f6e12fb6016cc3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63459
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Michał Żygowski 2022-04-07 15:07:46 +02:00 committed by Felix Held
parent a3cd3066ba
commit 79e61603dc
1 changed files with 8 additions and 0 deletions
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8
src/soc/intel/alderlake/include/soc/iomap.h
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@ -12,11 +12,19 @@
/*
* Memory-mapped I/O registers.
*/
#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_S)
#define PCH_PRESERVED_BASE_ADDRESS 0xfe000000
#define PCH_PRESERVED_BASE_SIZE 0x00800000
#define PCH_TRACE_HUB_BASE_ADDRESS 0xfd800000
#define PCH_TRACE_HUB_BASE_SIZE 0x00800000
#else
#define PCH_PRESERVED_BASE_ADDRESS 0xfc800000
#define PCH_PRESERVED_BASE_SIZE 0x02000000
#define PCH_TRACE_HUB_BASE_ADDRESS 0xfc800000
#define PCH_TRACE_HUB_BASE_SIZE 0x00800000
#endif
#define UART_BASE_SIZE 0x1000