soc/intel/skylake: use postcar stage for fsp 2.0
Utilize the postcar stage for tearing down CAR and initializing the MTRRs once ram is up. This flow is consistent with apollolake and allows CAR_GLOBAL variables to be directly accessed and no need for migrating CAR_GLOBAL variables as romstage doesn't run with and without CAR being available. Change-Id: I76de447710ae1d405886eb9420dc4064aa26eccc Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/19335 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Aaron Durbin
parent
5e88c3b18a
commit
79f0741f81
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@ -81,6 +81,8 @@ config USE_FSP2_0_DRIVER
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select PLATFORM_USES_FSP2_0
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select ADD_VBT_DATA_FILE
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select SOC_INTEL_COMMON_GFX_OPREGION
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select POSTCAR_CONSOLE
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select POSTCAR_STAGE
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config USE_FSP1_1_DRIVER
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bool "Build with FSP 1.1"
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@ -103,6 +103,11 @@ smm-$(CONFIG_SPI_FLASH_SMM) += spi.c
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smm-y += tsc_freq.c
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smm-$(CONFIG_UART_DEBUG) += uart_debug.c
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postcar-y += memmap.c
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postcar-y += monotonic_timer.c
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postcar-y += tsc_freq.c
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postcar-$(CONFIG_UART_DEBUG) += uart_debug.c
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# cpu_microcode_bins += ???
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CPPFLAGS_common += -I$(src)/soc/intel/skylake
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@ -20,7 +20,6 @@
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#include <arch/cpu.h>
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#include <fsp/api.h>
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asmlinkage void *car_stage_c_entry(void);
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void mainboard_memory_init_params(FSPM_UPD *mupd);
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void systemagent_early_init(void);
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int smbus_read_byte(unsigned int device, unsigned int address);
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@ -1,7 +1,6 @@
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verstage-y += power_state.c
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romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += car_stage.S
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romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += car_stage_fsp20.S
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romstage-y += pmc.c
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romstage-y += power_state.c
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romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += romstage.c
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@ -1,132 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2015-2016 Intel Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <rules.h>
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#include <cpu/x86/mtrr.h>
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#include <cpu/x86/cache.h>
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#include <cpu/x86/post_code.h>
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.section ".text"
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.global car_stage_entry
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car_stage_entry:
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/* Enter the C code */
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call car_stage_c_entry
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/*
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* Car teardown
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*/
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/*
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* eax: New stack address
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*/
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/* Switch to the stack in RAM */
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movl %eax, %esp
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/* chipset_teardown_car() is expected to disable cache-as-ram. */
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call chipset_teardown_car
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/* Display the MTRRs */
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call soc_display_mtrrs
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/*
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* The stack contents are initialized in src/soc/intel/common/stack.c
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* to be the following:
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*
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* *
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* *
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* *
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* +36: MTRR mask 1 63:32
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* +32: MTRR mask 1 31:0
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* +28: MTRR base 1 63:32
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* +24: MTRR base 1 31:0
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* +20: MTRR mask 0 63:32
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* +16: MTRR mask 0 31:0
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* +12: MTRR base 0 63:32
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* +8: MTRR base 0 31:0
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* +4: Number of MTRRs to setup (described above)
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* +0: Number of variable MTRRs to clear
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*/
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/* Clear all of the variable MTRRs. */
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popl %ebx
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movl $MTRR_PHYS_BASE(0), %ecx
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clr %eax
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clr %edx
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1:
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testl %ebx, %ebx
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jz 1f
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wrmsr /* Write MTRR base. */
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inc %ecx
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wrmsr /* Write MTRR mask. */
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inc %ecx
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dec %ebx
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jmp 1b
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1:
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/* Get number of MTRRs. */
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popl %ebx
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movl $MTRR_PHYS_BASE(0), %ecx
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2:
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testl %ebx, %ebx
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jz 2f
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/* Low 32 bits of MTRR base. */
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popl %eax
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/* Upper 32 bits of MTRR base. */
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popl %edx
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/* Write MTRR base. */
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wrmsr
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inc %ecx
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/* Low 32 bits of MTRR mask. */
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popl %eax
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/* Upper 32 bits of MTRR mask. */
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popl %edx
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/* Write MTRR mask. */
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wrmsr
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inc %ecx
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dec %ebx
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jmp 2b
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2:
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post_code(0x39)
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/* And enable cache again after setting MTRRs. */
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movl %cr0, %eax
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andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax
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movl %eax, %cr0
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post_code(0x3a)
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/* Enable MTRR. */
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movl $MTRR_DEF_TYPE_MSR, %ecx
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rdmsr
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orl $MTRR_DEF_TYPE_EN, %eax
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wrmsr
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post_code(0x3b)
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/* Invalidate the cache again. */
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invd
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__main:
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post_code(POST_PREPARE_RAMSTAGE)
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cld /* Clear direction flag. */
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call copy_and_run
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@ -115,7 +115,7 @@ static void save_dimm_info(void)
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printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt);
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}
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asmlinkage void *car_stage_c_entry(void)
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asmlinkage void car_stage_entry(void)
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{
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bool s3wake;
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struct postcar_frame pcf;
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@ -170,7 +170,7 @@ asmlinkage void *car_stage_c_entry(void)
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postcar_frame_add_mtrr(&pcf, 0xFFFFFFFF - CONFIG_ROM_SIZE + 1,
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CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT);
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return postcar_commit_mtrrs(&pcf);
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run_postcar_phase(&pcf);
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}
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static void cpu_flex_override(FSP_M_CONFIG *m_cfg)
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