From 79fe6a9537703458ff872e27ab9bc1d19c1380ea Mon Sep 17 00:00:00 2001 From: Lean Sheng Tan Date: Wed, 18 May 2022 17:58:39 +0200 Subject: [PATCH] mb/intel/ehlcrb: Adjust TSN GBE settings in devicetree Set PCH TSN link speed to 1 Gbps and enable MultiVC for all TSN ports. Signed-off-by: Lean Sheng Tan Change-Id: I8d43c3ba8f02645c8ad2993f76e610d838b0151a Reviewed-on: https://review.coreboot.org/c/coreboot/+/64478 Tested-by: build bot (Jenkins) Reviewed-by: Praveen HP Reviewed-by: Mario Scheithauer --- .../intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb index 8b075ff7bc..d3d114232d 100644 --- a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb +++ b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb @@ -153,8 +153,11 @@ chip soc/intel/elkhartlake }" # TSN GBE related UPDs - register "PchTsnGbeLinkSpeed" = "Tsn_2_5_Gbps" + register "PchTsnGbeLinkSpeed" = "Tsn_1_Gbps" register "PchTsnGbeSgmiiEnable" = "1" + register "PchTsnGbeMultiVcEnable" = "1" + register "PseTsnGbeMultiVcEnable[0]" = "1" + register "PseTsnGbeMultiVcEnable[1]" = "1" # GPIO for SD card detect register "sdcard_cd_gpio" = "GPP_G5"